An analytical solution to a double-gate MOSFET with undoped body
IBM1
TL;DR: In this paper, a 1D analytical solution for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poisson's equation was derived, giving closed forms of band bending and volume inversion as a function of silicon thickness and gate voltage.
Abstract: A one-dimensional (1-D) analytical solution is derived for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution gives closed forms of band bending and volume inversion as a function of silicon thickness and gate voltage. A threshold criterion is derived which serves to quantify the gate work function requirements for a double-gate CMOS.
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Book•
IBM1
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.
2,680 citations
TL;DR: In this article, a continuous analytic currentvoltage model for double-gate MOSFETs is presented, which is derived from closed-form solutions of Poisson's equation, and current continuity equation without the charge-sheet approximation.
Abstract: This letter presents a continuous analytic current-voltage (I-V) model for double-gate (DG) MOSFETs. It is derived from closed-form solutions of Poisson's equation, and current continuity equation without the charge-sheet approximation. The entire I/sub ds/(V/sub g/,V/sub ds/) characteristics for all regions of MOSFET operation: linear, saturation, and subthreshold, are covered under one continuous function, making it ideally suited for compact modeling. By preserving the proper physics, this model readily depicts "volume inversion" in symmetric DG MOSFETs-a distinctively noncharge-sheet phenomenon that cannot be reproduced by standard charge-sheet based I-V models. It is shown that the I-V curves generated by the analytic model are in complete agreement with two-dimensional numerical simulation results for all ranges of gate and drain voltages.
361 citations
Cites background from "An analytical solution to a double-..."
...Equation (1) can then be integrated twice to yield the solution [ 4 ]...
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...Note that the subthreshold current is proportional to the silicon thickness, but independent of —a manifestation of “volume inversion” [ 4 ] that cannot be reproduced by standard charge sheet-based I–V models....
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...a second-order effect ( 0.05 V) [ 4 ] coming from the term in (7)....
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IBM1
TL;DR: In this paper, a 1D analytic solution for symmetric and asymmetric double-gate MOSFETs was derived by incorporating only the mobile charge term in Poisson's equation.
Abstract: A one-dimensional (1-D) analytic solution is derived for an undoped (or lightly doped) double-gate (DG) MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution is applied to both symmetric and asymmetric DG MOSFETs to obtain closed forms of band bending and inversion charge as a function of gate voltage and silicon thickness. It is shown that for the symmetric DG device, "volume inversion" only occurs under subthreshold conditions, with a slightly negative impact on performance. Comparisons under the same off-state conditions show that the on-state inversion charge density of an asymmetric DG with one channel is only slightly less than that of a symmetric DG with two channels, if the silicon film is thin. From the analytic solutions, explicit expressions for the various components of the equivalent capacitance circuit are derived for symmetric and asymmetric DG devices. These help gain an insight into the electrostatic coupling between the back gate and the front channel in the asymmetric case. Finally, the gate work function requirements are quantified for symmetric and asymmetric DG CMOS, based on threshold voltage considerations.
357 citations
Cites methods from "An analytical solution to a double-..."
...In this paper, a one-dimensional (1-D) Poisson’s equation with only the inversion charge term is solved analytically for an undoped (or lightly doped) DG MOSFET [ 6 ]....
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TL;DR: In this article, a compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs is derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included.
Abstract: A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.
236 citations
Cites background from "An analytical solution to a double-..."
...As increases, the term reverses its sign, making the surface potential greater than the center potential, and the device enters a surface conduction mode, much similar to a bulk MOSFET [ 15 ]....
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...where is the electrostatic potential referenced to the Fermi level in the source [ 15 ], the electron density is given as...
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TL;DR: In this article, a general analytical subthreshold swing model for symmetric DG MOSFETs was derived using evanescent-mode analysis through a concept of effective conducting path, which explains a unique doping concentration (N/sub A/) dependence of S, providing a unified understanding of previous S models and leading to a new improved S model.
Abstract: A general analytical subthreshold swing (S) model for symmetric DG MOSFETs is derived using evanescent-mode analysis. Through a concept of effective conducting path, it explains a unique doping concentration (N/sub A/) dependence of S, providing a unified understanding of previous S models and leading to a new improved S model for undoped DG MOSFETs. Compact, explicit expressions of a scale length are derived, which expedite projections of scalability of DG MOSFETs and its requirement.
186 citations
References
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Book•
IBM1
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.
2,680 citations
"An analytical solution to a double-..." refers methods in this paper
...Here is the gate overdrive for the region of interest, and the last step used the expression , where is the silicon bandgap and are the effective densities of states [ 3 ]....
[...]
IBM1
TL;DR: In this article, the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations are discussed, including power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays.
Abstract: Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.
861 citations
"An analytical solution to a double-..." refers background in this paper
...For future CMOS logic circuits with a scaled-down power supply voltage [ 4 ], the above is too high....
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TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Abstract: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion. This original method of transistor operation offers excellent device performance, in particular great increases in subthreshold slope, transconductance, and drain current. A simulation program and experiments on SIMOX structures are used to study the new device.
729 citations
"An analytical solution to a double-..." refers background in this paper
...Among the advantages advocated for double-gate MOSFET’s are: ideal 60 mV/decade subthreshold slope, volume inversion [ 2 ], setting of threshold voltage by the gate work function thus avoiding dopants and associated number fluctuation effects, etc....
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IBM1
TL;DR: In this paper, Monte Carlo simulation is used to explore the characteristics of an n-channel MOSFET at the presently perceived limits of scaling, including a transconductance as high as 2300 mS/mm and an estimated ring-oscillator delay of 1.1 ps.
Abstract: Monte Carlo simulation is used to explore the characteristics of an n-channel MOSFET at the presently perceived limits of scaling. This dual-gated 30 nm gate-length FET is found to have excellent characteristics for use in digital logic, including a transconductance as high as 2300 mS/mm and an estimated ring-oscillator delay of 1.1 ps. The various motivations for this device design are discussed, illuminating the reasons for claiming that it is at the limits of scaling. >
287 citations