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Journal ArticleDOI

An approach to the design of RISC core processors for VLSI embedded systems

15 Mar 1997-Journal of Systems Architecture (North-Holland)-Vol. 43, Iss: 1, pp 33-37
TL;DR: A fully-pipelined RISC core processor for VLSI EAs adapted to real-time MPEG video compression together with the bottom-up design methodology used are presented in this paper.
About: This article is published in Journal of Systems Architecture.The article was published on 1997-03-15. It has received 2 citations till now. The article focuses on the topics: VHDL & Very-large-scale integration.
Citations
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Proceedings ArticleDOI
02 Nov 2003
TL;DR: The results of the experiments show that a large number of car or trucks accidents can be avoided by detecting real-time physical and psychological states of the drivers in normal driving conditions.
Abstract: In this work the most recent advances in digital image processing techniques has been used to make vehicle drivers face analysis by detecting symptoms of tiredness and distraction in order to prevent sudden risk situations. The results of the experiments show that a large number of car or trucks accidents can be avoided by detecting real-time physical and psychological states of the drivers in normal driving conditions. There are three main objectives in this design: To detect the driver eyelid movements, to detect the number of frames the driver has his eyes closed and to detect when the driver turns right or left (or bows) his head for a long time. Thus, several well known algorithms have been used and optimized for this field of application, such as spatial and temporal filtering, motion detection, optical flow analysis, etc. Digital signal and image processing techniques have been used together. Furthermore, a low-cost real-time solution based upon FPGA (ALTERA FLEX 10K30, field programmable gate array) has been achieved. Moreover, all the laboratory experiments are being carried out on real automobiles and a very low-cost, low-power and real-time solution based on ALTERA Cyclone Device (EP1C3) is available in the short-term.

26 citations

Journal ArticleDOI
TL;DR: A high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding and a macrocell for use in an ASIC has been designed and implemented using ES2 0.7 ?
Abstract: A high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding. A macrocell for use in an ASIC has been designed and implemented using ES2 0.7 ?m dual-layer-metal CMOS technology. This macrocell consists of about 120,000 equivalent gates and is able to execute, in real time, the Loop of an MPEG-2 coder for main profile/main level (MP@ML) resolution when running at 40 MHz. MViP is made up of several specific-purpose units (SPUs), an RISC core processor, banks of internal memory and an optimized crossbar network which lets these pipelined SPUs and RISC core work in parallel at a macroblock-level-pipeline, greatly increasing silicon efficiency.

9 citations


Cites methods from "An approach to the design of RISC c..."

  • ...The communication scheme between SPUs and RISCcore is obtained by means of interrupts....

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  • ...So, the RISCcore could also deal with external events like user commands or signals provided by other system units (e.g. the transmission buffer)....

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  • ...The RISCcore executes the instructions to control the different processes of the architecture performed by the SPUs and I/O units....

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  • ...Both the priority of the interrupts and the interrupt mask can be dynamically selected by the program running on the RISCcore....

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  • ...We have used this limit to design the SPUs and the RISCcore....

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References
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Book
01 Dec 1989
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Abstract: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high-performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and Web technologies, and high-performance computing.

11,671 citations

Book
01 Jan 1993
TL;DR: The third edition of the book as mentioned in this paper has been updated with new pedagogical features, such as new information and challenging exercises for the advanced student, as well as a complete index of the material in the book and on the CD appears in the printed index.
Abstract: What's New in the Third Edition, Revised Printing The same great book gets better! This revised printing features all of the original content along with these additional features:. Appendix A (Assemblers, Linkers, and the SPIM Simulator) has been moved from the CD-ROM into the printed book. Corrections and bug fixesThird Edition featuresNew pedagogical features.Understanding Program Performance -Analyzes key performance issues from the programmer's perspective .Check Yourself Questions -Helps students assess their understanding of key points of a section .Computers In the Real World -Illustrates the diversity of applications of computing technology beyond traditional desktop and servers .For More Practice -Provides students with additional problems they can tackle .In More Depth -Presents new information and challenging exercises for the advanced student New reference features .Highlighted glossary terms and definitions appear on the book page, as bold-faced entries in the index, and as a separate and searchable reference on the CD. .A complete index of the material in the book and on the CD appears in the printed index and the CD includes a fully searchable version of the same index. .Historical Perspectives and Further Readings have been updated and expanded to include the history of software R&D. .CD-Library provides materials collected from the web which directly support the text. In addition to thoroughly updating every aspect of the text to reflect the most current computing technology, the third edition .Uses standard 32-bit MIPS 32 as the primary teaching ISA. .Presents the assembler-to-HLL translations in both C and Java. .Highlights the latest developments in architecture in Real Stuff sections: -Intel IA-32 -Power PC 604 -Google's PC cluster -Pentium P4 -SPEC CPU2000 benchmark suite for processors -SPEC Web99 benchmark for web servers -EEMBC benchmark for embedded systems -AMD Opteron memory hierarchy -AMD vs. 1A-64 New support for distinct course goals Many of the adopters who have used our book throughout its two editions are refining their courses with a greater hardware or software focus. We have provided new material to support these course goals: New material to support a Hardware Focus .Using logic design conventions .Designing with hardware description languages .Advanced pipelining .Designing with FPGAs .HDL simulators and tutorials .Xilinx CAD tools New material to support a Software Focus .How compilers work .How to optimize compilers .How to implement object oriented languages .MIPS simulator and tutorial .History sections on programming languages, compilers, operating systems and databases On the CD.NEW: Search function to search for content on both the CD-ROM and the printed text.CD-Bars: Full length sections that are introduced in the book and presented on the CD .CD-Appendixes: Appendices B-D .CD-Library: Materials collected from the web which directly support the text .CD-Exercises: For More Practice provides exercises and solutions for self-study.In More Depth presents new information and challenging exercises for the advanced or curious student .Glossary: Terms that are defined in the text are collected in this searchable reference .Further Reading: References are organized by the chapter they support .Software: HDL simulators, MIPS simulators, and FPGA design tools .Tutorials: SPIM, Verilog, and VHDL .Additional Support: Processor Models, Labs, Homeworks, Index covering the book and CD contents Instructor Support Instructor support provided on textbooks.elsevier.com:.Solutions to all the exercises .Figures from the book in a number of formats .Lecture slides prepared by the authors and other instructors .Lecture notes

1,521 citations

Book
01 Jan 1981
TL;DR: A wrench having a fixed jaw and a movable jaw slidably mounted thereon, a cylindrical screw member rotatably mounted in an aperture formed on the base of the fixed jaw engaged with a rack on the movable Jaw means at each end and the base having sockets formed therein at said aperture.
Abstract: A wrench having a fixed jaw and a movable jaw slidably mounted thereon, a cylindrical screw member rotatably mounted in an aperture formed on the base of the fixed jaw engaged with a rack on the movable jaw, the screw member having a bore forming socket means at each end and the base having sockets formed therein at said aperture, a first ball member interposed between one socket of said base and the socket means on one end of said screw member and a second ball member interposed between one socket of said base and the socket means on the other end of said screw member and spring means urging each of said balls to the sockets of said base.

537 citations

Journal ArticleDOI
01 Feb 1995
TL;DR: An overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO is presented.
Abstract: The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures for DCT and block matching will be evaluated. Also dedicated decoder chips are included Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special, subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 /spl mu/m CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency. >

362 citations

Journal ArticleDOI
TL;DR: This paper explores the novel technical challenges in embedded system design and presents experiences and results of the work in this area using the CASTLE system, a central design representation for complex embedded systems and several analysis and visualization tools.
Abstract: In the past decade the main engine of electronic design automation has been the widespread application of ASICs (Application Specific Integrated Circuits). Present technology supports complete systems on a chip, most often used as so-called embedded systems in an increasing number of applications. Embedded systems pose new design challenges which we believe will be the driving forces of design automation in the years to come. These include the design of electronic systems hardware, embedded software and hardware / software codesign. This paper explores the novel technical challenges in embedded system design and presents experiences and results of the work in this area using the CASTLE system. CASTLE supports the design of complex embedded systems and the design of the required tools. It provides a central design representation, Verilog, VHDL and C/C++ frontends, Hardware generation in VHDL and BLIF, a retargetable compiler backend and several analysis and visualization tools. Two design examples, video compression and a diesel injection control, illustrate the presented concepts.

89 citations