An Effective Method to Compensate Total Ionizing Dose-Induced Degradation on Double-SOI Structure
TL;DR: In this article, double SOI was introduced to mitigate the radiation impact on fully depleted silicon-on-insulator (FDSOI) devices, and the impact of negative back-gate bias to transistor parameter degradation was investigated, and an improved backgate compensation strategy was proposed.
Abstract: The existence of buried oxide (BOX) layer and the strong coupling effect between the front and back channels can worsen the radiation-induced degradation on fully depleted silicon-on-insulator (FDSOI) device. To mitigate the radiation impact, a new structure named double SOI is introduced in this paper. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the BOX layer. With this structure, FDSOI device parameter degradation due to total dose is studied, and some abnormal phenomena, such as the transconductance hump and the mobility enhancement, are observed and discussed. Sentaurus TCAD simulations are used for further analysis. Moreover, the impact of negative back-gate bias to transistor parameter degradation is investigated, and an improved back-gate compensation strategy is proposed. Technology improvement such as thinning the BOX on total ionizing dose (TID) amelioration is also discussed with TCAD simulation.
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TL;DR: The results show that the OFF bias is relatively worse compared to other bias configurations for both NMOS and PMOS transistors, while the negative back bias of PMOS transistor can lead to both better performance and higher TID tolerance.
10 citations
TL;DR: The HfO 2 high-ĸ metal gate, the STI, and the PV dependent geometry were some of the influences that occurred within the degradation of electrical performances as the TID increased.
7 citations
TL;DR: In this paper, the dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity was investigated based on a 0.2- $\mu \text{m}$ double silicon-on-insulator (DSOI) technology.
Abstract: The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2- $\mu \text{m}$ double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LETth) for a DSOI 6T SRAM cell increases by 12.5% with back-gate bias of nMOS reduced from 0 to −15 V.
6 citations
01 Sep 2015
TL;DR: In this paper, the back transistors of the back transistor of SOI pMOSFETs were compared with those of the front transistors in a Float-State and Off-State bias during irradiation.
Abstract: The total dose radiation and annealing responses of the back transistor of Silicon-On-Insulator(SOI)pMOSFETs have been studied by comparing them with those of the back transistor of SOI n MOSFETs fabricated on the same wafer. The transistors were irradiated by60 Co γ-rays with various doses and the front transistors were biased in a Float-State and Off-State, respectively, during irradiation. The total dose radiation responses of the back transistors were characterized by their threshold voltage shifts. The results show that the total dose radiation response of the back transistor of SOI pMOSFETs, similar to that of SOI n MOSFETs, depends greatly on their bias conditions during irradiation. However, with the Float-State bias rather than the Off-State bias, the back transistors of SOI pMOSFETs reveal a much higher sensitivity to total dose radiation, which is contrary to the behavior of SOI n MOSFETs. In addition, it is also found that the total dose radiation effect of the back transistor of SOI pMOSFETs irradiated with Off-State bias, as well as that of the SOI n MOSFETs, increases as the channel length decreases. The annealing response of the back transistors after irradiation at room temperature without bias, as characterized by their threshold voltage shifts, indicates that there is a relatively complex annealing mechanism associated with channel length, type, and bias condition during irradiation. In particular, for all of the transistors irradiated with Off-State bias, their back transistors show an abnormal annealing effect during early annealing. All of these results have been discussed and analyzed in detail by the aid of simulation.
3 citations
01 Jan 2020
TL;DR: In this paper, two types of the MOSFET models available in commercial versions of TCAD and SPICE simulators are completed with additional equations taking into account radiation effects, and the adequacy of the models is demonstrated on two examples.
Abstract: Two types of the MOSFET models available in commercial versions of TCAD and SPICE simulators are completed with additional equations taking into account radiation effects. The adequacy of the models is demonstrated on two examples 1) 0.2 um and 0.24 um SOI/DSOI MOSFETs considering TID effects and single heavy ion impact, and 2) 28 nm bulk MOSFET, 45 nm and 28 nm high-k gate SOI MOSFETs considering TID effects.
3 citations
References
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31 Mar 1991
TL;DR: In this paper, the authors present a set of techniques for defect detection in SOI materials, including the following: 2.1.1 Silicon-on-Zirconia (SOZ), 2.2.2 E-beam recrystallization, 2.3.3, 3.4.4, and 3.5.5 Other defect assessment techniques.
Abstract: 1 Introduction.- 2 SOI Materials.- 2.1 Introduction.- 2.2 Heteroepitaxial techniques.- 2.2.1 Silicon-on-Sapphire (SOS).- 2.2.2 Other heteroepitaxial SOI materials.- 2.2.2.1 Silicon-on-Zirconia (SOZ).- 2.2.2.2 Silicon-on-Spinel.- 2.2.2.3 Silicon on Calcium Fluoride.- 2.3 Dielectric Isolation (DI).- 2.4 Polysilicon melting and recrystallization.- 2.4.1 Laser recrystallization.- 2.4.2 E-beam recrystallization.- 2.4.3 Zone-melting recrystallization.- 2.5 Homoepitaxial techniques.- 2.5.1 Epitaxial lateral overgrowth.- 2.5.2 Lateral solid-phase epitaxy.- 2.6 FIPOS.- 2.7 Ion beam synthesis of a buried insulator.- 2.7.1 Separation by implanted oxygen (SIMOX).- 2.7.1.1 "Standard"SIMOX.- 2.7.1.2 Low-dose SIMOX.- 2.7.1.3 ITOX.- 2.7.1.4 SMOXMLD.- 2.7.1.5 Related techniques.- 2.7.1.6 Material quality.- 2.7.2 Separation by implanted nitrogen (SIMNI).- 2.7.3 Separation by implanted oxygen and nitrogen (SIMON).- 2.7.4 Separation by implanted Carbon.- 2.8 Wafer Bonding and Etch Back (BESOI).- 2.8.1 Hydrophilic wafer bonding.- 2.8.2 Etch back.- 2.9 Layer transfer techniques.- 2.9.1 Smart-Cut(R).- 2.9.1.1 Hydrogen / rare gas implantation.- 2.9.1.2 Bonding to a stiffener.- 2.9.1.3 Annealing.- 2.9.1.4 Splitting.- 2.9.1.5 Further developments.- 2.9.2 Eltran(R).- 2.9.2.1 Porous silicon formation.- 2.9.2.2 The original Eltran(R) process.- 2.9.2.3 Second-generation Eltran(R) process.- 2.9.3 Transferred layer material quality.- 2.10 Strained silicon on insulator (SSOI).- 2.11 Silicon on diamond.- 2.12 Silicon-on-nothing (SON).- 3 SOI Materials Characterization.- 3.1 Introduction.- 3.2 Film thickness measurement.- 3.2.1 Spectroscopic reflectometry.- 3.2.2 Spectroscopic ellipsometry.- 3.2.3 Electrical thickness measurement.- 3.3 Crystal quality.- 3.3.1 Crystal orientation.- 3.3.2 Degree of crystallinity.- 3.3.3 Defects in the silicon film.- 3.3.3.1 Most common defects.- 3.3.3.2 Chemical decoration of defects.- 3.3.3.3 Detection of defects by light scattering.- 3.3.3.4 Other defect assessment techniques.- 3.3.3.5 Stress in the silicon film.- 3.3.4 Defects in the buried oxide.- 3.3.5 Bond quality and bonding energy.- 3.4 Carrier lifetime.- 3.4.1 Surface Photovoltage.- 3.4.2 Photoluminescence.- 3.4.3 Measurements on MOS transistors.- 3.4.3.1 Accumulation-mode transistor.- 3.4.3.2 Inversion-mode transistor.- 3.4.3.3 Bipolar effect.- 3.5 Silicon/Insulator interfaces.- 3.5.1 Capacitance measurements.- 3.5.2 Charge pumping.- 3.5.3 ?-MOSFET.- 4 SOI CMOS Technology.- 4.1 SOI CMOS processing.- 4.1.1 Fabrication yield and fabrication cost.- 4.2 Field isolation.- 4.2.1 LOCOS.- 4.2.2 Mesa isolation.- 4.2.3 Shallow trench isolation.- 4.2.4 Narrow-channel effects.- 4.3 Channel doping profile.- 4.4 Source and drain engineering.- 4.4.1 Silicide source and drain.- 4.4.2 Elevated source and drain.- 4.4.3 Tungsten clad.- 4.4.4 Schottky source and drain.- 4.5 Gate stack.- 4.5.1 Gate material.- 4.5.2 Gate dielectric.- 4.5.3 Gate etch.- 4.6 SOI MOSFET layout.- 4.6.1 Body contact.- 4.7 SOI-bulk CMOS design comparison.- 4.8 ESD protection.- 5 The SOI MOSFET.- 5.1 Capacitances.- 5.1.1 Source and drain capacitance.- 5.1.2 Gate capacitance.- 5.2 Fully and partially depleted devices.- 5.3 Threshold voltage.- 5.3.1 Body effect.- 5.3.2 Short-channel effects.- 5.4 Current-voltage characteristics.- 5.4.1 Lim & Fossum model.- 5.4.2 C?-continuous model.- 5.5 Transconductance.- 5.5.1 gm/ID ratio.- 5.5.2 Mobility.- 5.6 Basic parameter extraction.- 5.6.1 Threshold voltage and mobility.- 5.6.2 Source and drain resistance.- 5.7 Subthreshold slope.- 5.8 Ultra-thin SOI MOSFETs.- 5.8.1 Threshold voltage.- 5.8.2 Mobility.- 5.9 Impact ionization and high-field effects.- 5.9.1 Kink effect.- 5.9.2 Hot-carrier degradation.- 5.10 Floating-body and parasitic BJT effects.- 5.10.1 Anomalous subthreshold slope.- 5.10.2 Reduced drain breakdown voltage.- 5.10.3 Other floating-body effects.- 5.11 Self heating.- 5.12 Accumulation-mode MOSFET.- 5.12.1 I-V characteristics.- 5.12.2 Subthreshold slope.- 5.13 Unified body-effect representation.- 5.14 RF MOSFETs.- 5.15 CAD models for SOI MOSFETs.- 6 Other SOI Devices.- 6.1 Multiple-gate SOI MOSFETs.- 6.1.1 Multiple-gate SOI MOSFET structures.- 6.1.1.1 Double-gate SOI MOSFETs.- 6.1.1.2 Triple-gate SOI MOSFETs.- 6.1.1.3 Surrounding-gate SOI MOSFETs.- 6.1.1.4 Triple-plus gate SOI MOSFETs..- 6.1.2 Device characteristics.- 6.1.2.1 Current drive.- 6.1.2.2 Short-channel effects.- 6.1.2.3 Threshold voltage.- 6.1.2.4 Volume inversion.- 6.1.2.5 Mobility.- 6.2 MTCMOS/DTMOS.- 6.3 High-voltage devices.- 6.3.1 VDMOS and LDMOS.- 6.3.2 Other high-voltage devices.- 6.4 Junction Field-Effect Transistor.- 6.5 Lubistor.- 6.6 Bipolar junction transistors.- 6.7 Photodiodes.- 6.8 G4 FET.- 6.9 Quantum-effect devices.- 7 The SOI MOSFET in a Harsh Environment.- 7.1 Ionizing radiations.- 7.1.1 Single-event phenomena.- 7.1.2 Total dose effects.- 7.1.3 Dose-rate effects.- 7.2 High-temperature operation.- 7.2.1 Leakage current.- 7.2.2 Threshold voltage.- 7.2.3 Output conductance.- 7.2.4 Subthreshold slope.- 8 SOI Circuits.- 8.1 Introduction.- 8.2 Mainstream CMOS applications.- 8.2.1 Digital circuits.- 8.2.2 Low-voltage, low-power digital circuits.- 8.2.3 Memory circuits.- 8.2.3.1 Non volatile memory devices.- 8.2.3.2 Capacitorless DRAM.- 8.2.4 Analog circuits.- 8.2.5 Mixed-mode circuits.- 8.3 Niche applications.- 8.3.1 High-temperature circuits.- 8.3.2 Radiation-hardened circuits.- 8.3.3 Smart-power circuits.- 8.4 Three-dimensional integration.
1,627 citations
"An Effective Method to Compensate T..." refers background in this paper
...The Vtf is related to the back-gate threshold voltage variation induced by radiation and the back-gate bias, which can be expressed as [23], [24]...
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TL;DR: In this paper, an extensive set of experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures are presented, which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions.
Abstract: Accurate modeling of MOS devices requires quantitative knowledge of carrier mobilities in surface inversion and accumulation layers. Optimization of device structures and accurate circuit simulation, particulary as technologies push toward fundamental limits, necessitate an understanding of how impurity doping levels, oxide charge densities, process techniques, and applied electric fields affect carrier surface mobilities. It is the purpose of this paper to present an extensive set experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures. Empirical equations are developed which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions. The experimental results are interpreted in terms of the dominant physical mechanisms responsible for mobility degradation at the Si/SiO 2 interface. From the observed effects of process parameters on mobility roll-off under high vertical fields, conclusions are drawn about optimum process conditions for maximizing mobility. The implications of this work for performance limits of several types of MOS devices are described.
610 citations
TL;DR: An extensive set experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures are presented and empirical equations are developed which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions.
Abstract: Accurate modeling of MOS devices requires quantitative knowledge of carrier mobilities in surface inversion and accumulation layers. Optimization of device structures and accurate circuit simulation, particularly as technologies push toward fundamental limits, necessitate an understanding of how impurity doping levels, oxide charge densities, process techniques, and applied electric fields affect carrier surface nobilities. It is the purpose of this paper to present an extensive set of experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures. EmpiricaI equations are developed which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions. The experimental results are interpreted in terms of the dominant physical mechanisms responsible for mobility degradation at the Si/SiO/sub 2/ interface. From the observed effects of process parameters on mobility roll-off under high vertical fields, conclusions are drawn about optimum process conditions for maximizing mobility. The implications of this work for performance limits of several types of MOS devices are described.
284 citations
"An Effective Method to Compensate T..." refers background in this paper
...Since GMmax (near threshold voltage) is proportional to the carrier mobility [14], it means that the carrier mobility can be enhanced to a maximum value with positive trapped charges buildup in the BOX layer....
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...The weakened Eeff results in the enhanced GMmax [14]....
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...the enhancement of transconductance peak [14], [15]....
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TL;DR: In this paper, the radiation response of MOS devices exposed to /sup 60/Co and low-energy (approximately 10 keV) X-ray irradiation is evaluated as a function of electric field during exposure.
Abstract: The radiation response of MOS devices exposed to /sup 60/Co and low-energy ( approximately 10 keV) X-ray irradiation is evaluated as a function of electric field during exposure. Improved charge yield estimates are obtained for /sup 60/Co irradiations at fields below 1 MV/cm by matching voltage shifts due to oxide-trap and interface-trap charge to an E/sup -0.55/ electric field dependence. Combining these improved charge yield estimates and calculated dose enhancement factors, the relative response of X-ray to /sup 60/Co irradiations is accurately predicted for oxide electric fields from 0.03 MV/cm to 5.0 MV/cm. The ability to predict the relative response to X-ray to /sup 60/Co irradiations-should speed acceptance of X-ray testers as a hardness assurance tool. >
204 citations
"An Effective Method to Compensate T..." refers background in this paper
...However, at the same time, the negative-biased SOI2 can also enhance the electric field in the BOX1 layer, resulting in an acceleration of holes escaping the initial recombination, thereby increasing the probability of hole trapping [17]....
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TL;DR: In this article, the worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture, and experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.
Abstract: The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.
121 citations
"An Effective Method to Compensate T..." refers background or result in this paper
...Previous research has proved that the OFF-state was the worst bias condition for SOI nMOS transistors with floating body during irradiation [12], [13]....
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...tric influence, while trapping at the front interface under the body region determines back-gate transistor conduction [13]....
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...These parameters have been validated in [26] and [13]....
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