An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron Circuits
01 Jan 2016-pp 59-69
TL;DR: An algorithm which focus on the best possible combination of the input vector that reduce the leakage current without trying for all the possible 2 k combinations is proposed and shows a greater optimization in terms of time complexity and space complexity.
Abstract: Leakage current has a large impact in the performance of a system. Dominant component of the leakage current is the subthreshold leakage. One of the most sophisticated techniques for reducing leakage current is the transistor stack. Leakage current primarily depends upon the input vectors applied to the circuit. It is possible to demote the leakage current further with the usage of ‘IVC’. If it is possible to control this input vectors means leakage current can be reduced to a greater extent. A number of algorithms already exist to sort out this input vectors, but due to their exhaustive search nature they becomes ineffective. This paper propose an algorithm which focus on the best possible combination of the input vector that reduce the leakage current without trying for all the possible 2 k combinations. The problem can be treated as NP-Complete. Fan-out is not included in the algorithm since it is an independent factor of leakage current. The proposed algorithm precisely produces the input vector which gives the minimum leakage and shows a greater optimization in terms of time complexity and space complexity.
Citations
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06 Jul 2018
TL;DR: From the simulation results, it is clearly seen that the Subthreshold Leakage Reduction Ratio (SLRR) is high and proved the efficacy of the SPOGA technique in subthreshold leakage reduction.
Abstract: Low power consumption is the ultimate goal of the circuit designers of any application and specifically, the life time of event-driven nature of low duty cycle applications like Wireless Sensor Networks (WSN) relies on the design of power-stringent battery-operated devices. At all the hierarchical level of the sensor nodes, low duty cycling is the practicing solution in saving the unwanted power consumption. However, the rapid power squanderer at the sleep state of the circuit is the subthreshold leakage. The exact saving of the leakage can be done by suppressing the short-channel effects of the transistors only at the circuit-level and the two techniques Modified Power Gating (MPG) and Short-pulse POwer Gated Approach (SPOGA, hereafter called as SPOGA_old) are proposed and implemented in the combinational circuits in the previous works of the research. In spite of good subthreshold leakage reduction, the limitations of the proposed techniques are loading effect, state-retention and leakage estimation method. In order to provide an efficient sleep state subthreshold leakage reduction in combinational circuits of low duty cycle application, the limitations are addressed with a revisited design of SPOGA_old, called as SPOGA technique. The illustration of the proposed SPOGA technique with CMOS inverter is done using Cadence GPDK090. From the simulation results, it is clearly seen that the Subthreshold Leakage Reduction Ratio (SLRR) is high and proved the efficacy of the SPOGA technique in subthreshold leakage reduction.
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Cites background from "An Efficient Algorithm for Tracing ..."
...Philip et al [14] addressed the leakage reduction and proposed an algorithmic approach in which input vector minimum is used to find the best possible combination of vector inputs and reduced the leakage....
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References
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29 Apr 2003
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.
2,281 citations
10 Aug 1998
TL;DR: Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.
Abstract: Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by IISPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.
372 citations
05 May 1997
TL;DR: The proposed design changes consist of minimal overhead circuitry that puts the circuit into a "low leakage standby state", whenever it goes into standby, and allows it to return to its original state when it is reactivated.
Abstract: In order to reduce the power dissipation of CMOS products, semiconductor manufacturers are reducing the power supply voltage. This requires that the transistor threshold voltages be reduced as well to maintain adequate performance and noise margins. However, this increases the subthreshold leakage current of p and n MOSFETs, which starts to offset the power savings obtained from power supply reduction. This problem will worsen in future generations of technology, as threshold voltages are reduced further. In order to overcome this, we propose a design technique that can be used during logic design in order to reduce the leakage current and power. We target designs where parts of the circuit are put in "standby" mode when not in use, which is becoming a common approach for low power design. The proposed design changes consist of minimal overhead circuitry that puts the circuit into a "low leakage standby state", whenever it goes into standby, and allows it to return to its original state when it is reactivated. We give an efficient algorithm for computing a good low leakage power state. We demonstrate this method on the ISCAS-89 benchmark suite and show leakage power reductions of up to 54% for some circuits.
298 citations
TL;DR: Two runtime mechanisms for reducing the leakage current of a CMOS circuit are described and a design technique for applying the minimum leakage input to a sequential circuit is presented, which shows that it is possible to reduce the leakage by an average of 25% with practically no delay penalty.
Abstract: The first part of this paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" signal is used to shift in a new set of external inputs and pre-selected internal signals into the circuit with the goal of setting the logic values of all of the internal signals so as to minimize the total leakage current in the circuit. This minimization is possible because the leakage current of a CMOS gate is strongly dependent on the input combination applied to its inputs. In the second method, nMOS and pMOS transistors are added to some of the gates in the circuit to increase the controllability of the internal signals of the circuit and decrease the leakage current of the gates using the "stack effect". This is, however, done carefully so that the minimum leakage is achieved subject to a delay constraint for all input-output paths in the circuit. In both cases, Boolean satisfiability is used to formulate the problems, which are subsequently solved by employing a highly efficient SAT solver. Experimental results on the combinational circuits in the MCNC91 benchmark suite demonstrate that it is possible to reduce the leakage current in combinational circuits by an average of 25% with only a 5% delay penalty. The second part of this paper presents a design technique for applying the minimum leakage input to a sequential circuit. The proposed method uses the built-in scan-chains in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. The use of these scan registers eliminates the area and delay overhead of the additional circuitry that would otherwise be needed to apply the minimum leakage vector to the circuit. Experimental results on the sequential circuits in the MCNC91 benchmark suit show that, by using the proposed method, it is possible to reduce the leakage by an average of 25% with practically no delay penalty.
293 citations
TL;DR: Methods for estimating leakage at the circuit level are outlined and a heuristic and exact algorithms to accomplish the same task for random combinational logic are proposed.
Abstract: Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I/sub D/DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.
199 citations