An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron Circuits
01 Jan 2016-pp 59-69
TL;DR: An algorithm which focus on the best possible combination of the input vector that reduce the leakage current without trying for all the possible 2 k combinations is proposed and shows a greater optimization in terms of time complexity and space complexity.
Abstract: Leakage current has a large impact in the performance of a system. Dominant component of the leakage current is the subthreshold leakage. One of the most sophisticated techniques for reducing leakage current is the transistor stack. Leakage current primarily depends upon the input vectors applied to the circuit. It is possible to demote the leakage current further with the usage of ‘IVC’. If it is possible to control this input vectors means leakage current can be reduced to a greater extent. A number of algorithms already exist to sort out this input vectors, but due to their exhaustive search nature they becomes ineffective. This paper propose an algorithm which focus on the best possible combination of the input vector that reduce the leakage current without trying for all the possible 2 k combinations. The problem can be treated as NP-Complete. Fan-out is not included in the algorithm since it is an independent factor of leakage current. The proposed algorithm precisely produces the input vector which gives the minimum leakage and shows a greater optimization in terms of time complexity and space complexity.
Citations
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06 Jul 2018
TL;DR: From the simulation results, it is clearly seen that the Subthreshold Leakage Reduction Ratio (SLRR) is high and proved the efficacy of the SPOGA technique in subthreshold leakage reduction.
Abstract: Low power consumption is the ultimate goal of the circuit designers of any application and specifically, the life time of event-driven nature of low duty cycle applications like Wireless Sensor Networks (WSN) relies on the design of power-stringent battery-operated devices. At all the hierarchical level of the sensor nodes, low duty cycling is the practicing solution in saving the unwanted power consumption. However, the rapid power squanderer at the sleep state of the circuit is the subthreshold leakage. The exact saving of the leakage can be done by suppressing the short-channel effects of the transistors only at the circuit-level and the two techniques Modified Power Gating (MPG) and Short-pulse POwer Gated Approach (SPOGA, hereafter called as SPOGA_old) are proposed and implemented in the combinational circuits in the previous works of the research. In spite of good subthreshold leakage reduction, the limitations of the proposed techniques are loading effect, state-retention and leakage estimation method. In order to provide an efficient sleep state subthreshold leakage reduction in combinational circuits of low duty cycle application, the limitations are addressed with a revisited design of SPOGA_old, called as SPOGA technique. The illustration of the proposed SPOGA technique with CMOS inverter is done using Cadence GPDK090. From the simulation results, it is clearly seen that the Subthreshold Leakage Reduction Ratio (SLRR) is high and proved the efficacy of the SPOGA technique in subthreshold leakage reduction.
1 citations
Cites background from "An Efficient Algorithm for Tracing ..."
...Philip et al [14] addressed the leakage reduction and proposed an algorithmic approach in which input vector minimum is used to find the best possible combination of vector inputs and reduced the leakage....
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References
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TL;DR: A divide-and-conquer approach is presented that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits to overcome the limitation of internal gates at high logic levels.
Abstract: Input vector control (IVC) is a popular technique for leakage power reduction. It utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector (MLV) to the primary inputs of combinational circuits during the standby mode. However, the IVC technique becomes less effective for circuits of large logic depth because the input vector at primary inputs has little impact on leakage of internal gates at high logic levels. In this paper, we propose a technique to overcome this limitation by replacing those internal gates in their worst leakage states by other library gates while maintaining the circuit's correct functionality during the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction when the MLV is not effective. We then present a divide-and-conquer approach that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits. Our experimental results on all the MCNC91 benchmark circuits reveal that 1) the gate replacement technique alone can achieve 10% leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; and 3) compared with the leakage achieved by optimal MLV in small circuits, the gate replacement heuristic and the divide-and-conquer approach can reduce on average 13% and 17% leakage, respectively.
85 citations
11 Sep 2002
TL;DR: The results indicate that using a such a generic SAT solver can improve on previously proposed random approaches, and the solver is called as a post-process to a random-vector-generation approach.
Abstract: Leakage current promises to be a major contributor to power dissipation in future technologies. Bounding the maximum and minimum leakage current poses an important problem. Determining the maximum leakage ensures that the chip meets power dissipation constraints. Applying an input pattern that minimizes leakage allows extending battery life when the circuit is in standby mode. Finding such vectors can be expressed as a satisfiability problem. We apply in this paper an incremental SAT solver, PBS [1], to find the minimum or maximum leakage current. The solver is called as a post-process to a random-vector-generation approach. Our results indicate that using a such a generic SAT solver can improve on previously proposed random approaches [7].
78 citations
TL;DR: Two novel approaches to leakage power minimization in static complementary metal-oxide-semiconductor circuits that employ input vector control (IVC) are investigated, and the heuristic MLP approach is shown to be approximately 13.6 times faster than the exact ILP method, whereas finding input vectors whose power consumption is only a few percent above the optimum.
Abstract: Leakage power consumption is an increasingly serious problem in very large-scale integration circuits, especially for portable applications. Two novel approaches to leakage power minimization in static complementary metal-oxide-semiconductor circuits that employ input vector control (IVC) are investigated. The authors model leakage effects by means of pseudo-Boolean functions. These functions are linearized and incorporated into an exact (optimal) integer linear programming (ILP) model, called virtual-gate ILP, which analyzes leakage variation with respect to a circuit's input vectors. A heuristic mixed-integer linear programming (MLP) method is also proposed, which has several advantages: it is faster, its accuracy can be quickly estimated, and tradeoffs between runtime and optimality can easily be made. Furthermore, the MLP model also provides a way to estimate a lower bound on circuit leakage current. The proposed methods are used to generate an extensive set of experimental results on leakage reduction. It is shown that average leakage currents are usually 1.25 times the minimum, confirming the effectiveness of IVC. The heuristic MLP approach is shown to be approximately 13.6 times faster than the exact ILP method, whereas finding input vectors whose power consumption is only a few percent above the optimum. In addition, the lower bound estimated by the MLP model is also within a few percent of the optimal value
36 citations
07 Jun 2004
TL;DR: This paper presents an algorithm for computing minimal switching cost partial input vectors such that the leakage of the circuit is always less than the upper bound, and extends the MLS algorithm to compute a bounded leakage set (BLS).
Abstract: In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identify the minimum leakage set of input vectors (MLS). Applying a vector in the MLS is known as Input Vector Control (IVC), and has proven to be very useful in reducing gate oxide leakage and sub-threshold leakage in standby mode of operation. The approach presented here is based on Implicit Enumeration of integer-valued decision diagrams. Since the search space for minimum leakage vector increases exponentially with the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. To reduce the switching power dissipated when the inputs are driven to a given state (during entry into and exit from the standby state), we extend the MLS algorithm to compute a bounded leakage set (BLS). Given a bound of standby leakage, we present an algorithm for computing minimal switching cost partial input vectors such that the leakage of the circuit is always less than the upper bound.
35 citations