# An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron Circuits

01 Jan 2016-pp 59-69

TL;DR: An algorithm which focus on the best possible combination of the input vector that reduce the leakage current without trying for all the possible 2 k combinations is proposed and shows a greater optimization in terms of time complexity and space complexity.

Abstract: Leakage current has a large impact in the performance of a system. Dominant component of the leakage current is the subthreshold leakage. One of the most sophisticated techniques for reducing leakage current is the transistor stack. Leakage current primarily depends upon the input vectors applied to the circuit. It is possible to demote the leakage current further with the usage of ‘IVC’. If it is possible to control this input vectors means leakage current can be reduced to a greater extent. A number of algorithms already exist to sort out this input vectors, but due to their exhaustive search nature they becomes ineffective. This paper propose an algorithm which focus on the best possible combination of the input vector that reduce the leakage current without trying for all the possible 2 k combinations. The problem can be treated as NP-Complete. Fan-out is not included in the algorithm since it is an independent factor of leakage current. The proposed algorithm precisely produces the input vector which gives the minimum leakage and shows a greater optimization in terms of time complexity and space complexity.

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06 Jul 2018TL;DR: From the simulation results, it is clearly seen that the Subthreshold Leakage Reduction Ratio (SLRR) is high and proved the efficacy of the SPOGA technique in subthreshold leakage reduction.

Abstract: Low power consumption is the ultimate goal of the circuit designers of any application and specifically, the life time of event-driven nature of low duty cycle applications like Wireless Sensor Networks (WSN) relies on the design of power-stringent battery-operated devices. At all the hierarchical level of the sensor nodes, low duty cycling is the practicing solution in saving the unwanted power consumption. However, the rapid power squanderer at the sleep state of the circuit is the subthreshold leakage. The exact saving of the leakage can be done by suppressing the short-channel effects of the transistors only at the circuit-level and the two techniques Modified Power Gating (MPG) and Short-pulse POwer Gated Approach (SPOGA, hereafter called as SPOGA_old) are proposed and implemented in the combinational circuits in the previous works of the research. In spite of good subthreshold leakage reduction, the limitations of the proposed techniques are loading effect, state-retention and leakage estimation method. In order to provide an efficient sleep state subthreshold leakage reduction in combinational circuits of low duty cycle application, the limitations are addressed with a revisited design of SPOGA_old, called as SPOGA technique. The illustration of the proposed SPOGA technique with CMOS inverter is done using Cadence GPDK090. From the simulation results, it is clearly seen that the Subthreshold Leakage Reduction Ratio (SLRR) is high and proved the efficacy of the SPOGA technique in subthreshold leakage reduction.

1 citations

### Cites background from "An Efficient Algorithm for Tracing ..."

...Philip et al [14] addressed the leakage reduction and proposed an algorithmic approach in which input vector minimum is used to find the best possible combination of vector inputs and reduced the leakage....

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##### References

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16 Apr 2007

TL;DR: In this approach, the authors selectively modify a gate so that its output (in sleep mode) is in a state which helps minimize the leakage of other gates in its transitive fanout.

Abstract: Leakage power currently comprises a large fraction of the total power consumption of an IC. Techniques to minimize leakage have been researched widely. In this paper, the authors present an approach which minimizes leakage by simultaneously modifying the circuit while deriving the input vector that minimizes leakage. In this approach, the authors selectively modify a gate so that its output (in sleep mode) is in a state which helps minimize the leakage of other gates in its transitive fanout. Gate replacement is performed in a slack-aware manner, to minimize the resulting delay penalty

23 citations

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01 Jan 2007

10 citations

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25 Mar 2012TL;DR: Simulation results show that the efficiency of the proposed algorithm increases by increasing the number of input vector, and it is characterized as faster than other algorithms, its speed doubles strongly of other algorithms speed when theNumber of circuit inputs increases.

Abstract: Due to the significance of leakage power for CMOS circuits at Nanoscale, a new technique for Sub-threshold leakage current reduction based on Input vector control (IVC) is proposed. The proposed algorithm is called Fast Input Vector Algorithm (FIVA). It is characterized as faster than other algorithms, its speed doubles strongly of other algorithms speed when the number of circuit inputs increases. Simulation results show that the efficiency of the proposed algorithm increases by increasing the number of input vector. For 2-bits Full Adder, FIVA has speed up reaches 70%. For 8-bits Full Adder, FIVA has speed up reaches 97%, which validates the proposed algorithm.

10 citations

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TL;DR: This article proposes a fast heuristic algorithm to find a low-leakage input vector with simultaneous gate replacement that produces 14% better leakage current reduction with several orders of magnitude speedup in runtime for large circuits compared to the previous state-of-the-art algorithm.

Abstract: The Input vector control (IVC) technique is based on the observation that the leakage current in a CMOS logic gate depends on gate input state, and a good input vector is able to minimize leakage when the circuit is in sleep mode. The gate replacement technique is a very effective method to further reduce the leakage current. In this article, we propose a fast heuristic algorithm to find a low-leakage input vector with simultaneous gate replacement. Results on MCNC91 benchmark circuits show that our algorithm produces 14p better leakage current reduction with several orders of magnitude speedup in runtime for large circuits compared to the previous state-of-the-art algorithm. In particular, the average runtime for the ten largest combinational circuits has been dramatically reduced from 1879 seconds to 0.34 seconds.

7 citations

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12 Mar 2015TL;DR: This paper presents MLV for various test circuits using genetic algorithm implemented in Verilog HDL to obtain MLV and explores that heuristic approaches can be considered as better algorithms in finding optimum solution.

Abstract: Leakage power dissipation plays a major role in the total power dissipation with the advancement in the technology. Reduction of leakage power is of top concern in the present trend of nanotechnology. Input Vector Control (IVC) is one of the approaches used for static power reduction during standby mode. Leakage in a circuit depends on input vector applied at primary inputs due to stacking effect. Minimum leakage vector (MLV) is the input vector to which a circuit can offer a minimum leakage for a given set of test inputs. This paper presents MLV for various test circuits using genetic algorithm. The algorithm is implemented in Verilog HDL to obtain MLV. Results explores that heuristic approaches can be considered as better algorithms in finding optimum solution. Another advantage found during simulation is that implementation of algorithm in HDL converges in less number of iterations with runtime savings compared to random search method.

4 citations