An Efficient Method for Fast Delay and SI Calculation Using Current Source Models
17 Mar 2008-pp 57-61
TL;DR: The transient simulation cost of a stage with a single driver can be reduced from O(kmn3) to O(kn) with a small runtime overhead by applying diagonalization and Sherman-Morrison formula together with a one-step Newton-Raphson method.
Abstract: Current source models are the methods of choice for gate-level delay and SI calculation in Deep Sub Micron regime. To fully utilize the information provided by the current source models, numerical integration is often applied to solve stage-based transient simulation that calculates delay, slew, or noise bumps. However, this is computationally expensive. In this paper, we present a fast and robust algorithm for delay and signal integrity (SI) calculation using current source models. By applying diagonalization and Sherman-Morrison formula together with a one-step Newton-Raphson method, the transient simulation cost of a stage with a single driver can be reduced from O(kmn3) to O(kn) with a small runtime overhead, where k is the number of time step, m is the average number of Newton-Raphson steps, and n is the size of matrices of the Reduced Order Model(ROM) of the parasitic network. The proposed method works perfectly with the popular implicit integration methods such as the Trapezoidal and Backward Euler method.
Citations
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08 Jun 2008
TL;DR: The paper discusses the challenges introduced by the new high accuracy models and techniques to ameliorate them for Library providers.
Abstract: The Liberty Format is an open source industry standard for library modeling that has seen significant enhancement in recent years to address the challenges introduced by the new smaller technologies at 65 nm and below. Issues associated with modeling Timing, Power and Noise have seen an explosion in complexity. The paper discusses the challenges introduced by the new high accuracy models and techniques to ameliorate them for Library providers.
16 citations
07 Sep 2010
TL;DR: A novel method for generating current source models for logic cells that efficiently captures the influences of parameter variation and supply voltage drops and exploits topological information from the transistor netlist resulting in typically 80x faster CSM library generation.
Abstract: This paper presents a novel method for generating current source models (CSMs) for logic cells that efficiently captures the influences of parameter variation and supply voltage drops. The characterization exploits topological information from the transistor netlist resulting in typically 80x faster CSM library generation. The parametric CSMs have been integrated into a commercial FastSPICE simulator to further accelerate path-based timing analysis with transistor level accuracy. Without loss of accuracy, simulation times were reduced by 4x to 98x.
5 citations
Cites methods from "An Efficient Method for Fast Delay ..."
...EDA vendors recognized the importance of precise waveform modeling for correct delay modeling and introduced the new driver and delay models ECSM and CCS [1, 2, 24 ]....
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01 Jan 2012
TL;DR: Chapter 4 presents various dedicated methods that support variability handling in the design process so that the designer can analyze the effect of variations on his design and identify possible improvements.
Abstract: Chapter 4 presents various dedicated methods that support variability handling in the design process. Using these methods, the designer can analyze the effect of variations on his design and identify possible improvements.
4 citations
16 Mar 2009
TL;DR: Standard cell libraries are used extensively in CMOS digital circuit designs and in the past ten years, standard cell library size has increased by more than 10X.
Abstract: Standard cell libraries are used extensively in CMOS digital circuit designs. In the past ten years, standard cell library size has increased by more than 10X. Reducing the library size is becoming a must.
1 citations
References
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02 Jun 2003
TL;DR: Blade is a novel cell model and runtime engine based on current flow and Razor is the accompanying interconnect model that produce and consume arbitrary voltage waveforms with near-SPICE accuracy at speeds tens of thousands of times faster than SPICE.
Abstract: In order to adequately account for nanometer effects during timing analysis, archaic standard cell models must be replaced. Simplifying assumptions used during characterization, such as nearly linear voltage inputs or lumped-capacitance loads, are no longer valid. Signal integrity analysis further complicates the characterization process because the typical voltage waveform used during characterization does not contain a noise component. This paper introduces two new technologies for standard cell and interconnect timing analysis: Blade and Razor. Blade is a novel cell model and runtime engine based on current flow. Razor is the accompanying interconnect model. Both Blade and Razor produce and consume arbitrary voltage waveforms with near-SPICE accuracy at speeds tens of thousands of times faster than SPICE.
142 citations
"An Efficient Method for Fast Delay ..." refers methods in this paper
...To achieve good analysis accuracy with the current source models, more complex calculation scheme is needed to fully utilize the current source model information [ 2 ,3,4]....
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06 Jun 1994
TL;DR: A new empirical gate delay model is proposed which combines the benefits of empirically derived k-factor models and switch-resistor models to efficiently handle capacitance shielding due to metal interconnect resistance, model the RC interconnect delay, and provide tighter bounds for simultaneous switching.
Abstract: As signal speeds increase and gate delays decrease for high-performance digital integrated circuits, the gate delay modeling problem becomes increasingly more difficult. With scaling, increasing interconnect resistances and decreasing gate-output impedances make it more difficult to empirically characterize gate-delay models. Moreover, the single-input-switching assumption for the empirical models is incompatible with the inevitable simultaneous switching for today.s high-speed logic paths. In this paper a new empirical gate delay model is proposed. Instead of building the empirical equations in terms of capacitance loading and input-signal transition time, the models are generated in terms of parameters which combine the benefits of empirically derived k-factor models and switch-resistor models to efficiently: 1) handle capacitance shielding due to metal interconnect resistance, 2) model the RC interconnect delay, and 3)provide tighter bounds for simultaneous switching.
111 citations
"An Efficient Method for Fast Delay ..." refers methods in this paper
...The commonly used NLDM constant C_effective based calculation [ 5 ] is not good enough for the current source models, because the C_effective based calculation assumes a constant driver output effective capacitance....
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27 Mar 2006
TL;DR: This work constructs current-based gate models based on the existing Liberty timing library format without further pre-characterization, and presents an inverse problem formulation, and proposes to solve the problem by quadratic polynomial regression.
Abstract: Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires additional pre-characterization of the gate, e.g., in the form of a new or an extended timing library format. We construct current-based gate models based on the existing Liberty timing library format without further pre-characterization. We present an inverse problem formulation, and propose to solve the problem by quadratic polynomial regression. Our constructed current-based gate models find applications in timing, power, and signal integrity verifications for improved accuracy in library-compatible flows, e.g., to include power supply voltage drop effect in gate delay calculation without further pre-characterization, to calculate gate supply current, etc. Our experimental results show our constructed current-based gate models achieve slightly less accurate results, e.g., within 4.6%(8.6%), than pre-characterized current-based gate models, e.g., within 4.3%(4.4%), of SPICE results in gate delay calculation for ideal (degraded) power supply voltage, and accurate gate supply current calculation.
18 citations
"An Efficient Method for Fast Delay ..." refers methods in this paper
...To achieve good analysis accuracy with the current source models, more complex calculation scheme is needed to fully utilize the current source model information [2,3, 4 ]....
[...]
06 Mar 2006
TL;DR: A cell delay model based on rate-of-current-change is presented, which accounts for the impact of the shape of the noisy waveform on the output voltage waveform.
Abstract: A cell delay model based on rate-of-current-change is presented, which accounts for the impact of the shape of the noisy waveform on the output voltage waveform. More precisely, a pre-characterized table of time derivatives of the output current as a function of input voltage and output load values is constructed. The data in this table, in combination with the Taylor series expansion of the output current, is utilized to progressively compute the output current waveform, which is then integrated to produce the output voltage waveform. Experimental results show the effectiveness and efficiency of this new delay model.
2 citations
"An Efficient Method for Fast Delay ..." refers methods in this paper
...To achieve good analysis accuracy with the current source models, more complex calculation scheme is needed to fully utilize the current source model information [2, 3 ,4]....
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