An Energy-Efficient 3Gb/s PAM4 Full-Duplex Transmitter With 2-Tap Feed Forward Equalizer
02 Apr 2020-IEEE Transactions on Circuits and Systems Ii-express Briefs (Institute of Electrical and Electronics Engineers (IEEE))-Vol. 67, Iss: 5, pp 916-920
TL;DR: A full-duplex 3 Gb/s PAM4 voltage-mode transmitter with an embedded 2-tap feed forward equalizer with an echo canceller achieves energy proportionality with output swings and equalizer coefficients.
Abstract: We present a full-duplex 3 Gb/s PAM4 voltage-mode transmitter with an embedded 2-tap feed forward equalizer. In full-duplex mode, the transmitter employs an echo canceller to cancel the locally transmitted signal and recover the signal from the far-end. The transmitter achieves energy proportionality with output swings and equalizer coefficients. Fabricated in 65 nm Digital CMOS process, the transmitter transmits a maximum of 1 V peak-to-peak differential output swing. In full-duplex mode, the transmitter equalizes 2 m UTP cable and dissipates 37.3 mW at 3Gb/s with echo canceller in the receiver path. The power reduces to 18.3 mW while transmitting across a 9 m UTP cable in the half-duplex mode.
Citations
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TL;DR: In this article , a power-efficient half-rate current-integrating logic (CIL) echo cancelation hybrid circuit topology was proposed for full-duplex communication for off-chip interconnects in 65 nm CMOS.
Abstract: This work proposes a power‐efficient half‐rate current‐integrating logic (CIL) echo cancelation hybrid circuit topology for full‐duplex communication for off‐chip interconnects in 65 nm CMOS. The proposed hybrid topology has a low power consumption compared to traditional current‐mode hybrid circuit topology implementations, thanks to the CIL hybrid topology with sample and hold front‐end. The post‐layout performance of the half‐rate CIL hybrid includes package parasitic has a differential received signal voltage swing of 190 mV at 10 Gb/s data rate with a timing jitter of 16 ps over a 20 cm FR4 PCB interconnect. The total power consumption of the half‐rate CIL hybrid is only 2 mW, and its energy efficiency is 0.4 pJ/bit. The layout of the hybrid occupies an area of 0.0008 mm2.
1 citations
TL;DR: Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed.
Abstract: This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed.
1 citations
Additional excerpts
...In [16], an energy proportional PAM4 voltage-mode equalizer with 2-tap FIR equalization was proposed for full-duplex transmission....
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28 May 2022
TL;DR: In this article , a low-power half-rate charge-steering echo cancellation hybrid circuit topology is proposed for full-duplex signaling over chip-to-chip interconnects.
Abstract: In this paper, a low-power half-rate charge-steering echo cancellation hybrid circuit topology is proposed for full-duplex signaling over chip-to-chip interconnects. The proposed half-rate charge-steering hybrid topology has a very low power consumption compared to traditional current-mode and voltage-mode hybrid circuit topology implementations, thanks to the discrete nature of charge-steering hybrid topology avoiding direct current path between V DD and ground. The half-rate hybrid circuit topology has been implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout performance of the half-rate charge-steering hybrid including package parasitic has a differential received signal voltage swing of 0.8 V at 10 Gb/s data rate with a timing jitter of 10 ps over a FR4 PCB interconnect of length 20 cm. The total power consumption of the half-rate charge-steering hybrid is only 0.16 mW and its energy efficiency is 0.032 pJ/bit. The layout of the hybrid occupies an area of 0.0007 mm 2 .
TL;DR: 3 link configurations are discussed from the view of tradeoff between the link performance and cost, illustrating that the COM based ML modeling method can be applied to advanced serial link design for NRZ, PAM4 or even other higher level pulse amplitude modulation signal.
Abstract: SUMMARY This paper presents a channel operating margin (COM) based high-speed serial link optimization using machine learning (ML). COM that is proposed for evaluating serial link is calculated at first and dur- ing the calculation several important equalization parameters corresponding to the best configuration are extracted which can be used for the ML modeling of serial link. Then a deep neural network containing hidden layers are investigated to model a whole serial link equalization including transmitter feed forward equalizer (FFE), receiver continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE). By training, val- idating and testing a lot of samples that meet the COM specification of 400GAUI-8 C2C, an e ff ective ML model is generated and the maximum relative error is only 0.1 compared with computation results. At last 3 link configurations are discussed from the view of tradeo ff between the link per- formance and cost, illustrating that our COM based ML modeling method can be applied to advanced serial link design for NRZ, PAM4 or even other higher level pulse amplitude modulation signal.
28 May 2022
TL;DR: In this article , an energy efficient current-mode hybrid circuit topology for echo cancellation was proposed for full-duplex signalling over chip-to-chip interconnects, which consists of only two transconductors, transmitter and replica generator.
Abstract: In this paper, an energy efficient current-mode hybrid circuit topology for echo-cancellation is proposed for full-duplex signalling over chip-to-chip interconnects. Conventional full-duplex transceivers consists of three transcondutors, namely, for transmitting the outbound signal, for replica generation and for cancellation or subtraction, leading to an increase in the power consumption. However, the proposed hybrid circuit topology consists of only two transconductors, transmitter and replica generator. The separation of the inbound signal from the signal on the line is achieved using a simple resistor, thereby eliminating the need of additional transconductor for subtraction. This makes the proposed hybrid an attractive choice for realizing power efficient full-duplex transceiver compared to the existing transceiver with current-mode and voltage-mode hybrid circuit topologies. The proposed hybrid is implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout simulation including the package parasitic has a differential received signal voltage swing of 85 mV at 10 Gb/s data rate over a 20-cm FR4 PCB trace. The total power consumption of the hybrid is 0.29 mW and the corresponding energy efficiency is 0.057 pJ/bit. The layout of the hybrid occupies an area of 0.00025 mm 2 .
References
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TL;DR: A dual-mode NRZ/PAM4 serial I/O SerDes which can support both modulations with minimum power and hardware overhead relative to a dedicated PAM4 link is presented.
Abstract: While four-level pulse amplitude modulation (PAM4) standards are emerging to increase bandwidth density, the majority of standards use simple binary non-return-to-zero (NRZ) signaling. This paper presents a dual-mode NRZ/PAM4 serial I/O SerDes which can support both modulations with minimum power and hardware overhead relative to a dedicated PAM4 link. A source-series-terminated transmitter achieves 1.2- $\text{V}_{\mathrm {{pp}}}$ output swing and employs lookup table control of a 31-segment output digital-to-analog converter (DAC) to implement 4/2-tap feed-forward equalization in NRZ/PAM4 modes, respectively. Transmitter power is improved with low-overhead analog impedance control in the DAC cells and a quarter-rate serializer based on a tri-state inverter-based mux with dynamic pre-driver gates. The receiver implements an NRZ/PAM4 decision feedback equalizer that employs one finite impulse response and two infinite impulse response taps for first post-cursor and long-tail inter-symbol interference (ISI) cancellation, respectively. First post-cursor ISI cancellation is performed in these comparators to optimize the design’s timing, while the remaining ISI taps are subtracted in a preceding current integration summer for improved sensitivity. Fabricated in GP 65-nm CMOS, the transceiver occupies 0.074 mm2 area and achieves 16 Gb/s NRZ and 32 Gb/s PAM4 operation at 10.9 and 5.5 mW/Gb/s while operating over channels with 27.6 and 13.5 dB loss at Nyquist, respectively.
78 citations
"An Energy-Efficient 3Gb/s PAM4 Full..." refers background in this paper
...In contrast, standard PAM4 VM O/P driver [5] or look-up-table based source series terminated PAM4 equalizer [6] has incurred severe power penalty in the output driver and pre-driver....
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19 Mar 2015
TL;DR: A dual-mode transmitter implemented in 14nm CMOS that supports both NRZ and PAM4 modulations and operates from 16 to 40Gb/s is presented.
Abstract: Emerging standards in wireline communication are defining a path to data-rates of 40Gb/s and beyond. Most previous standards for these networking applications use NRZ signaling. However, practical signal integrity constraints have led to a renewed interest in also supporting PAM4 for some applications and loss profiles [1-2]. Recently, several transmitters have been reported that operate between 28 and 60Gb/s using NRZ or PAM4 modulation exclusively [2-4]. However, high-speed SerDes building blocks that support both a wide frequency range and multiple forms of modulation provide more compatibility between components and avoid the development of multiple IPs. In addition, these blocks must continue to scale into the next-generation of CMOS process technologies to lower the cost by reducing area and power consumption. This paper presents a dual-mode transmitter (TX) implemented in 14nm CMOS that supports both NRZ and PAM4 modulations and operates from 16 to 40Gb/s. The TX incorporates a 4-tap NRZ FIR filter that is reconfigurable to drive PAM4 levels, quarter-rate clocking with a high-bandwidth 4:1 serializer, a duty-cycle and quadrature-error correction circuit with statistical phase error detection, and compact, multi-layer T-coils for pad capacitance (C pad ) reduction.
63 citations
"An Energy-Efficient 3Gb/s PAM4 Full..." refers background in this paper
...In contrast, standard PAM4 VM O/P driver [5] or look-up-table based source series terminated PAM4 equalizer [6] has incurred severe power penalty in the output driver and pre-driver....
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TL;DR: Using a shunt branch in parallel with the differential channel to implement pre-emphasis is shown to have the best overall energy-efficiency, and an efficient pre- emphasis voltage mode transmitter architecture with output amplitude control, pre-phasis coefficient control, and online impedance calibration is proposed and demonstrated.
Abstract: This paper analyzes the signaling and digital power overhead of pre-emphasis voltage-mode transmitters. Utilizing a shunt branch in parallel with the differential channel to implement pre-emphasis is shown to have the best overall energy-efficiency. Leveraging this technique, an efficient pre-emphasis voltage mode transmitter architecture with output amplitude control, pre-emphasis coefficient control, and online impedance calibration is proposed and demonstrated. A 65 nm LP CMOS implementation of this architecture dissipates ~ 10 mW from a 1.2 V supply when transmitting 10 Gb/s 200 mV differential amplitude data with 2-tap pre-emphasis, achieving 1 pJ/bit energy efficiency.
44 citations
"An Energy-Efficient 3Gb/s PAM4 Full..." refers background in this paper
...During equalization, VM O/P drivers with constant current consumption, current inversely proportional to the output swing, and current directly proportional to the output swing [4] have been realized for PAM2 modulation....
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12 Jun 2003
TL;DR: In this article, a low-power self-terminated transmitter is proposed to perform impedance matching and channel equalization with low power consumption, which operates at 3.6 Gbps and consumes 9.66 mW.
Abstract: This paper describes a low-power self-terminated transmitter. A novel architecture is proposed to perform impedance matching and channel equalization with low power consumption. The test chip is fabricated using 0.18-/spl mu/m digital CMOS process with 1.8-V supply. The transmitter operates at 3.6 Gbps and consumes 9.66 mW. The total transmitter area is 0.072 mm/sup 2/.
38 citations
"An Energy-Efficient 3Gb/s PAM4 Full..." refers methods in this paper
...The architecture is derived from a conventional voltage-mode output driver with 2-tap equalization for the NRZ modulation scheme [7]....
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22 Sep 2014
TL;DR: A duplex architecture coupled with a linear Class-AB push-pull output stage that maximizes the power efficiency of linear wideband drivers for high-speed transceivers and enables adaptive echo cancellation and rail-to-rail full-duplex operation is detailed.
Abstract: Gigabit Ethernet PHY (GPHY) transceivers find wide use in SoCs and standalone PHY chips with hundreds of millions of ports shipped every year. Transceiver design has recently focused on power reduction driven by the need for higher port density and throughput with minimum energy and thermal cost. The line drivers that deliver power from a high voltage supply to remote 100Ω differential loads dominate the GPHY power consumption. The supply voltage determined by the transmit amplitude specs (e.g., 2Vppdiff for 1000BASE-T/100BASE-TX Ethernet) does not scale with technology. This paper presents an architecture that enables rail-to-rail full-duplex operation for high voltage efficiency resulting in a 2.5V GPHY driver in 28nm CMOS that saves 24% power from the mainstream 3.3V drivers.
14 citations
"An Energy-Efficient 3Gb/s PAM4 Full..." refers background in this paper
...But, such a full-duplex architecture requires large loop gain and bandwidth for low residual error after removal [3]....
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