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An entropy measure for the complexity of multi-output Boolean functions

Kwang-Ting Cheng, +1 more
- pp 302-305
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TLDR
Experimental data is presented in support of the entropy definition of computational work based upon the input-output description of a Boolean function and circuit delay is shown to have a non-linear relationship to the computational work.
Abstract
Entropy measures are examined in view of the current logic synthesis methodology. The complexity of a Boolean function can be expressed in terms of computational work. Experimental data are presented in support of the entropy definition of computational work based upon the input-output description of a Boolean function. These data show a linear relationship between the computational work and the average number of literals in a multilevel implementation. The investigation includes single-output and multioutput function with and without don't care states. The experiments conducted on a large number of randomly generated functions showed that the effect of don't cares is to reduce the computational work. For several finite state machine benchmarks, the computational work gave a good estimate of the size of the circuit. Circuit delay is shown to have a nonlinear relationship to the computational work. >

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Citations
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High-level power modeling, estimation, and optimization

TL;DR: This paper surveys representative contributions to power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow that have appeared in the recent literature.
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Towards a high-level power estimation capability

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High-level power modeling, estimation, and optimization

TL;DR: A non-exhaustive survey of the mostsuccessful and innovative ideas in this area that have appeared in the literature in the last few years is provided.
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High-level power estimation

TL;DR: The state of the art in high-level power estimation is surveyed in this article, addressing techniques that operate at the architecture, behavior, instruction, and system levels of abstraction, e.g., at the instruction level.
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Towards a high-level power estimation capability [digital ICs]

TL;DR: A power estimation technique for digital integrated circuits that operates at the register transfer level (RTL) that is based on the use of entropy as a measure of the average activity to be expected in the final implementation of a circuit, given only its Boolean functional description.
References
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Journal ArticleDOI

MIS: A Multiple-Level Logic Optimization System

TL;DR: An overview of the MIS system and a description of the algorithms used are provided, including some examples illustrating an input language used for specifying logic and don't-cares.
Journal ArticleDOI

MUSTANG: state assignment of finite state machines targeting multilevel logic implementations

TL;DR: The authors present state-assignment algorithms that heuristically maximize the number of common cubes in the encoded network to maximize theNumber of literals in the resulting combinational logic network after multilevel logic optimization.
Journal ArticleDOI

An Information Theoretic Approach to Digital Fault Testing

TL;DR: The concepts of information theory are applied to the problem of testing digital circuits by analyzing the information throughput of the circuit and an expression for the probability of detecting a hardware fault is derived.
Journal ArticleDOI

A Measure of Computational Work

TL;DR: The relation between the work of a process and the work capacity of a facility on which it is implemented is examined, and a concept of efficiency of implementations is formulated.
Journal ArticleDOI

Information theory and the complexity of boolean functions

TL;DR: The complexity of approximately realizing a partially specified Boolean function, in whose table a fractiond of the entries are unspecified and a fractionp of the specified entries are l's with errors allowed in a fraction not more thane of thespecified entries, is less by the factor (1 −d) [H(p) − H(e]].