Journal ArticleDOI
An error efficient and low complexity approximate multi-bit adder for image processing applications
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TLDR
The proposed 16‐bit approximate carry select adder (CSLA) shows a significant reduction of 58% in area delay product and 70% in power delay product, in comparison with the conventional CSLA, and the image metrics results validate that the proposed adder with highest peak signal‐to‐noise ratio is highly adoptable for image processing applications.About:
This article is published in International Journal of Circuit Theory and Applications.The article was published on 2021-06-03. It has received 7 citations till now. The article focuses on the topics: Adder & Image processing.read more
Citations
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Journal ArticleDOI
A stochastic computing architecture for local contrast and mean image thresholding algorithm
TL;DR: An energy‐efficient and fault‐tolerant architecture is proposed for implementing the LCM algorithm in stochastic computing (SC), leveraging correlated input bitstreams to save energy and improve the fault tolerance of the implementation.
Journal ArticleDOI
Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending
TL;DR: This work presents three base adders using the novel concept of error tolerance in digital VLSI design that exhibit reduced delay, power dissipation, area, powerdelay product (PDP), energy delay product (EDP), and area delay product(ADP) compared to the existing approximate adders.
Proceedings ArticleDOI
Review of Approximate Computing in Image Processing Applications
TL;DR: In this article , a bit truncated Pseudo-8T Static Random Access Memory (BT-PSRAM) is proposed for compressed multimedia applications, and gives encouraging result with low power and energy consumption.
Proceedings ArticleDOI
Run Time Power and Accuracy Management with Approximate Circuits
TL;DR: In this paper , a methodology to trade off accuracy with run-time power consumption through Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs) is proposed.
Proceedings ArticleDOI
Performance Evaluation of Fault-Tolerant Approximate Adder
T. Mendez,Subramanya G. Nayak +1 more
TL;DR: Three designs of fault-tolerant adders Selector Based Fault-Tolerant Adder-I (SBFTA-I), Selector based Fault- Tolerant adder-II (SBfTA-II) and Optimized Fault- tolerance Adder (OFTA) are proposed and implemented in this work with reduced switching activity and gate count.
References
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Journal ArticleDOI
A Survey of Techniques for Approximate Computing
TL;DR: A survey of techniques for approximate computing (AC), which discusses strategies for finding approximable program portions and monitoring output quality, techniques for using AC in different processing units, processor components, memory technologies, and so forth, as well as programming frameworks for AC.
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Approximate Computing: A Survey
TL;DR: This paper presents a survey of state-of-the-art work in all aspects of approximate computing and highlights future research challenges in this field.
Journal ArticleDOI
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing
TL;DR: A novel error-tolerant adder (ETA) is proposed that is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance.
Proceedings ArticleDOI
Invited - Cross-layer approximate computing: from logic to architectures
TL;DR: This paper provides a systematical understanding of how to generate and explore the design space of approximate components, which enables a wide-range of power/energy, performance, area and output quality tradeoffs, and a high degree of design flexibility to facilitate their design.
Proceedings ArticleDOI
A Comparative Review and Evaluation of Approximate Adders
TL;DR: Simulation results show that the equal segmentation adder (ESA) is the most hardware-efficient design, but it has the lowest accuracy in terms of error rate (ER) and mean relative error distance (MRED).