An FPGA-Based High-Speed Error Resilient Data Aggregation and Control for High Energy Physics Experiment
TL;DR: A novel orthogonal concatenated code and cyclic redundancy check have been used to mitigate the effects of data corruption in the user data and a novel memory management algorithm is proposed that helps to process the data at the back-end computing nodes removing the added path delays.
Abstract: Due to the dramatic increase of data volume in modern high energy physics (HEP) experiments, a robust high-speed data acquisition (DAQ) system is very much needed to gather the data generated during different nuclear interactions. As the DAQ works under harsh radiation environment, there is a fair chance of data corruption due to various energetic particles like alpha, beta, or neutron. Hence, a major challenge in the development of DAQ in the HEP experiment is to establish an error resilient communication system between front-end sensors or detectors and back-end data processing computing nodes. Here, we have implemented the DAQ using field-programmable gate array (FPGA) due to some of its inherent advantages over the application-specific integrated circuit. A novel orthogonal concatenated code and cyclic redundancy check (CRC) have been used to mitigate the effects of data corruption in the user data. Scrubbing with a 32-b CRC has been used against error in the configuration memory of FPGA. Data from front-end sensors will reach to the back-end processing nodes through multiple stages that may add an uncertain amount of delay to the different data packets. We have also proposed a novel memory management algorithm that helps to process the data at the back-end computing nodes removing the added path delays. To the best of our knowledge, the proposed FPGA-based DAQ utilizing optical link with channel coding and efficient memory management modules can be considered as first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, bit error rate, efficiency, and robustness to radiation.
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TL;DR: The proposed CRC algorithm can reduce the error rate of the system by detecting and controlling the errors, and the validity of CRC algorithm is verified by experiments.
5 citations
Journal Article•
TL;DR: The main advancement of the work is the use of modified BCH(15, 11) code that leads to high error correction capabilities for burst errors and user friendly packet length.
Abstract: This paper presents the design of a compact pro- tocol for fixed-latency, high-speed, reliable, serial transmission between simple field-programmable gate arrays (FPGA) devices. Implementation of the project aims to delineate word boundaries, provide randomness to the electromagnetic interference (EMI) generated by the electrical transitions, allow for clock recov- ery and maintain direct current (DC) balance. An orthogonal concatenated coding scheme is used for correcting transmission errors using modified Bose–Chaudhuri–Hocquenghem (BCH) code capable of correcting all single bit errors and most of the double-adjacent errors. As a result all burst errors of a length up to 31 bits, and some of the longer group errors, are corrected within 256 bits long packet. The efficiency of the proposed solution equals 46.48%, as 119 out of 256 bits are fully available to the user. The design has been implemented and tested on Xilinx Kintex UltraScale+ KCU116 Evaluation Kit with a data rate of 28.2 Gbps. Sample latency analysis has also been performed so that user could easily carry out calculations for different transmission speed. The main advancement of the work is the use of modified BCH(15, 11) code that leads to high error correction capabilities for burst errors and user friendly packet length.
1 citations
Cites methods from "An FPGA-Based High-Speed Error Resi..."
...Authors in [5] propose high-speed error resilient communication protocol intended to be used in HEP experiments....
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TL;DR: In this article , a detailed literature survey on state-of-the-art machine learning methods for NPP equipment condition assessment is presented, including major failure modes, data sources, maintenance strategies, and relationship between equipment lifetime, assessment technology, and maintenance strategy.
Abstract: Abstract The condition assessment of equipment in nuclear power plants (NPPs) could provide essential information for operation and maintenance decisions, which would have a significant impact on improving the safety and economy of NPPs. To date, substantial work has been conducted on the condition assessment based on machine learning for NPP equipment. To provide a comprehensive overview for researchers interested in developing machine learning methods for NPP equipment condition assessment, this critical review presents a detailed literature survey on state-of-the-art research and identifies challenges for future study. Valuable information is presented, including major failure modes, data sources, maintenance strategies, and the relationship between equipment lifetime, assessment technology, and maintenance strategy. Following the typical lifetime of NPP equipment for condition assessment, current works in this domain are categorized into anomaly detection, remaining useful life prediction, and fault detection and diagnosis. The techniques and methodologies adopted in the literature are summarized from each aspect. In particular, the in-depth NPP equipment condition assessment survey based on deep learning methods is presented. In addition, we elaborate on current issues, challenges, and future research directions for the condition assessment of equipment in NPPs. These directions we believe will pave the way for equipment condition assessment.
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TL;DR: A modular development framework that can be adapted for different systems by simply changing the software or firmware parts, based on the demands of the system to be developed.
Abstract: System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, http, Java, and LabView for control and communication, together with the MicroC/OS-II and OSE operating systems
24 citations
31 Dec 2012
TL;DR: An FPGA implementation of a custom network interface for an optical link between PCIe buses of compute nodes and a bandwidth of 8.5 Gbit/s was achieved between software applications, exceeding bandwidth reported in recent work.
Abstract: To achieve speedup for multi-node, multi-GPU computing platforms, it is necessary to overcome performance bottlenecks in networks based on Ethernet or Infiniband. This paper describes an FPGA implementation of a custom network interface for an optical link between PCIe buses of compute nodes. The implementation uses an Altera Stratix IV chip with integrated PCIe interface logic and high-speed input/output for connecting optical fiber interfaces. The interface is designed with control and buffering for concurrent data transfers. A software driver enables application programs on the host computer to use the high-speed link. A bandwidth of 8.5 Gbit/s was achieved between software applications, exceeding bandwidth reported in recent work [7].
23 citations
"An FPGA-Based High-Speed Error Resi..." refers methods in this paper
...[5], where they have used PCIe hard IP available in the ALTERA Stratix IV FPGA board....
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01 Nov 2016-Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment
TL;DR: This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and its adaptation for the STS and MUCH detector's conditions and a specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip.
Abstract: The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.
22 citations
"An FPGA-Based High-Speed Error Resi..." refers background in this paper
...1, SOS, and EOS are received in proper sequence or not and then received characters are sent to the command decoder block....
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...1, start of synchronization (SOS), and end of synchronization (EOS) [22] will be exchanged before sending the hit data from the FEB to the OIB....
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...After that, the OIB sends EOS to FEBs and the synchronization process will complete when all FEBs properly respond with EOS....
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24 May 2010
TL;DR: A PCIe card and front-end cards equipped with the small form-factor pluggable (SFP) transceivers for the data transfer via optical fiber and a new protocol has been designed and implemented on the FPGAs in order to provide communication between the PCI card and the front- end cards.
Abstract: Future experiments at the new accelerator facility FAIR (Facility for Antiproton and Ion Research) for the research with ion and anti-proton beams require new developments of front-end electronics to tolerate high data rate. We have developed a PCIe card and front-end cards equipped with the small form-factor pluggable (SFP) transceivers for the data transfer via optical fiber. A new protocol has been designed and implemented on the FPGAs in order to provide communication between the PCIe card and the front-end cards. The standard data acquisition (DAQ) system at GSI, multi-branch system (MBS), has been upgraded to support the PCIe cards and is working stably with the data transfer rate up to 180 Mbytes per second.
22 citations
"An FPGA-Based High-Speed Error Resi..." refers methods in this paper
...[4] developed a gigabit optical serial interface protocol for communication over optical fiber and implemented peripheral component interconnect express (PCIe) to optical link interface in the FPGA for the DAQ system with a stable data rate of 1....
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09 Nov 2003
TL;DR: In this article, the authors present a short overview of optical fiber communication systems and the challenges that face one from a modeling, analysis and design perspective, and describe novel formulations and computational techniques for the analysis of the interplay between the information signals and the optical noise due to the fiber nonlinearity as they propagate together along the fiber link.
Abstract: The optical fiber transmission links form the backbone of the communications infrastructure. Almost all of voice and data (internet) traffic is routed through terrestrial and submarine optical fiber links, connecting the world together. Invention of the optical amplifiers (OAs) and wavelength-division multiplexing (WDM) technology enabled very high capacity optical fiber communication links that run for thousands of kilometers without any electronic repeaters, but at the same time brought many design challenges. As electronic amplifiers do, OAs add noise to the signal they amplify. In the design of an optical fiber communication link, the prediction of the deterioration the information signals experience due to the nonlinearity of the optical fiber and the optical noise generated by the OAs is essential. In this paper, we first present a short overview of optical fiber communication systems and the challenges that faces one from a modeling, analysis and design perspective. Then, we describe novel formulations and computational techniques for the analysis of the interplay between the information signals and the optical noise due to the fiber nonlinearity as they propagate together along the fiber link. Our formulations are similar, in spirit, to the linear(ized), time-varying formulations for noise analysis in analog/RF electronic circuits. We then investigate signal-noise mixing due to optical fiber nonlinearities using the techniques developed. Finally, we discuss the use of the generated results in the performance evaluation of communication links, and comment on system design implications.
9 citations
"An FPGA-Based High-Speed Error Resi..." refers background in this paper
...Noise in optical network obeys Poisson statistics [26], so the noise (i....
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