An FPGA configuration circuit used for fast and partial configuration
01 Oct 2007-pp 157-160
TL;DR: An improved architecture used for FPGA's fast and partial configuration is proposed, designed based on a 32 bits wide data bus, which can be controlled by a set of instructions.
Abstract: An improved architecture used for FPGA's fast and partial configuration is proposed. It is designed based on a 32 bits wide data bus, which can be controlled by a set of instructions. A partial control register and an address decoding logic are added in this design. Multiple configuration interfaces could be connected in this architecture, making hardware updating fast and convenient. Comparing with Virtex Series FPGA's configuration architecture, produced by Xilinx Corp., which only can configure memory cells by frame, this new architecture could configure any single memory cell in FPGA, offering more flexible configuration operations.
Citations
More filters
01 Nov 2008
TL;DR: A configuration circuit used in the FDP (FDP: Fu Dan Programmable device) FPGA chip could write configuration data into FDP and read back data from FDP successfully, providing more flexible configuration operations.
Abstract: This paper presents a configuration circuit used in the FDP (FDP: Fu Dan Programmable device) FPGA chip. This circuit could write configuration data into FDP and read back data from FDP successfully. Comparing with Xilinx Virtex Series FPGA chips, the smallest configuration section of which is one data-frame, the proposed circuit could write each single memory cell in FDP, providing more flexible configuration operations. A standard configuration interface, Serial Peripheral Interface (SPI), is added in this circuit to replace using the expensive Xilinx Platform configuration Flash PROMs. A group of high precise sensitive amplifiers is adopted in this configuration circuit, which are used to magnify the read back data values. Through a novel write/read asynchronous FIFO structure in FDP, which divides the external interface and internal configuration circuit into two clock domains, designers could set the external clock and internal clock separately. Basic functions of the configuration circuit have been correctly verified by Altera DE2 development board platform. The post layout simulation results indicate via this configuration circuit, each data frame in FDP could be written in 4 mus, and could be read back in 5 mus. The total configuration time of FDP chip is about 6.5 ms.
9 citations
Cites background or methods from "An FPGA configuration circuit used ..."
...3) in FDP FPGA could indentify the configuration value of each memory cell in a vertical frame([9])....
[...]
...Companying with the address decoder in figure 4, which could identify the data frame in a CLB column at a horizontal position, each single memory cell in FDP FPGA could be written separately([9])....
[...]
...If each memory cell at a data frame in an FPGA could be written separately, when updating one data frame which contains dynamic memory contents by readback and writeback operations, designer could only revise the desirable data values in this frame without stoping FPGA operation since any data that represents the dynamic memory contents will not be written back into memory cells([9]) ....
[...]
...Unlike Virtex Series FPGA, a group of partial configuration control logic and a partial configuration control register([9]) are added in FDP (high lighted in Fig....
[...]
01 Aug 2013
TL;DR: A SPI FLASH-based FPGA dynamic reconfiguration method according to the principle of FPGAs configuration is designed and the results show that this design is reasonably practicable and has achieved the design requirements of dynamic reconfigurement.
Abstract: To make the FPGA configuration more flexible and easier, this article designs a SPI FLASH-based FPGA dynamic reconfiguration method according to the principle of FPGA configuration. In the paper, some of the key technologies in software design are analyzed and solved. Besides, the design has been verified on the hardware platform as well. The results show that this design is reasonably practicable and has achieved the design requirements of dynamic reconfiguration.
6 citations
11 Dec 2009
TL;DR: The post layout simulation shows that this fast configuration circuit of FDP2009-II-SOPC FPGA could work correctly and efficiently and the configuration time is less than 53% of that of Xilinx VirtexII series FPG a1.
Abstract: In this paper, fast configuration architecture of FPGA suitable for bitstream compression is proposed and implemented for FDP2009-II-SOPC (FDP2009-II-SOPC: Fudan Programmable device 2009-II-SOPC) FPGA with SMIC 0.13 CMOS process. This circuit features an addressable configuration register and the internal frame decoder that makes a 32-bit memory cell of FPGA addressable. The improved configuration circuit which can configuration every 32bit memory cells could provide faster configuration speed and more flexible partial configuration operations. The die size of FDP2009-II-SOPC is about 6.3mm*4.5mm=28.35mm2 and the area of this configuration circuit is about 1.7mm2. The post layout simulation shows that this fast configuration circuit of FDP2009-II-SOPC FPGA could work correctly and efficiently and the configuration time is less than 53% of that of Xilinx VirtexII series FPGA1.
4 citations
01 Oct 2012
TL;DR: A novel circuit architecture for configuration bitstream compression based on JTAG is proposed, which decompresses and compresses bitstream while FPGA is configured and performs readback accordingly.
Abstract: A novel circuit architecture for configuration bitstream compression based on JTAG is proposed. The circuit decompresses and compresses bitstream while FPGA is configured and performs readback accordingly. The compression and decompression operations are implemented dynamically by a concise hardware architecture within the framework of IEEE standard 1149.1. Run Length Encode/Decode (RLE/D) algorithm is used for compression coding. Using Chartered 0.13um single-poly-8-metal process, the chip size is 0.01 mm2.
4 citations
Cites methods from "An FPGA configuration circuit used ..."
...Using Chartered 0.13um single-poly-8-metal process, the chip size is 0.01 mm2 ....
[...]
25 May 2009
TL;DR: An FPGA configuration circuit based on JTAG is designed which has the JTAG architecture which is compatible with the IEEE standard 1149.1.
Abstract: An FPGA configuration circuit based on JTAG is designed. The configuration circuit has the JTAG architecture which is compatible with the IEEE standard 1149.1. Under the shift function of JTAG, a data chain for configuration is provided. The process of the configuration is controlled by three simple counters. Implemented with the CSMC 0.5um technology, the configuration circuit has the area of 1.404mm2, occupies the 3 percent of total FPGA area. Compared with the control scheme of complex state machine, this design is simple and has been used in an FPGA.
3 citations
References
More filters
TL;DR: To realize high-density SRAMs, a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS is developed and an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability is developed.
Abstract: To realize high-density SRAMs, we developed a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS The vertical poly-silicon PMOS has a gate surrounding a body that forms a channel and yields a drive current of 20 /spl mu/A at 25/spl deg/C Vertical poly-silicon PMOSs are used as transfer MOSs and are stacked over the bulk NMOSs, used as driver MOSs, to reduce the size of a four-transistor SRAM cell As a result, the size of the proposed four-transistor SRAM cell was 38% of that of a six-transistor SRAM cell We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability
24 citations
"An FPGA configuration circuit used ..." refers methods in this paper
...After partial configuration frame and configuration frame is downloaded, the control state machine asserts both Write_Ctrl signal which is a control signal of partial configuration logic and Write_Enable signal which is a frame address control signal to control the two access transistors’ gates of the six-transistor memory cell([5]), then the configuration information will be written into memory cells or not....
[...]
01 Jan 2006
TL;DR: The way of loading the bit file into the FPGA chip, which has been taped out with SMIC 0.18mum CMOS process this year, and MODELSIM is used to verify the design before and after the layout is generated.
Abstract: The most charming feature of FPGA is that it is post-fabricated, which means that user can design his own logic onto the chip without the need of tape out. So both design cycle and prototype cost can be greatly reduced. Once the bit file - which is a binary file representing the user designed logic s generated, it should be downloaded into the chip to realize the user logic. This paper deals with the way of loading the bit file into the FPGA chip, which has been taped out with SMIC 0.18mum CMOS process this year. Daisy chain and CRC check circuits are designed in this FPGA chip. We use MODELSIM to verify the design before and after the layout is generated. The area of downloading circuit is less than 3 percent of the whole chip
6 citations