An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IBM1
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
Abstract: The D-algorithm (DALG) is shown to be ineffective for the class of combinational logic circuits that is used to implement error correction and translation (ECAT) functions. PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits. PODEM uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems. It is shown that PODEM is very efficient for ECAT circuits and is significantly more efficient than DALG over the general spectrum of combinational logic circuits. A distinctive feature of PODEM is its simplicity when compared to the D-algorithm. PODEM is a complete algorithm in that it will generate a test if one exists. Heuristics are used to achieve an efficient implicit search of the space of all possible primary input patterns until either a test is found or the space is exhausted.
Citations
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08 May 1989
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Abstract: A set of 31 digital sequential circuits described at the gate level is presented. These circuits extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-based test generation, and mixed sequential/scan-based test generation using partial scan techniques. Although all the benchmark circuits are sequential, synchronous, and use only D-type flip-flops, additional interior faults and asynchronous behavior can be introduced by substituting for some or all of the flip-flops their appropriate functional models. The standard functional model of the D flip-flop provides a reference point that is independent of the faults particular to the flip-flop implementation. A testability profile of the benchmarks in the full-scan-mode configuration is discussed. >
1,972Â citations
Book•
01 Jul 1990
TL;DR: In this article, a wheel decorating ornament comprising an annular, planar sheet of material decorated on opposite sides, axially disposed between the groups of spokes and radially disposed at the rim and the hub, is presented.
Abstract: In combination with a wheel for a bicycle and the like having an annular rim, a hub rotatable about its axis, and axially offset groups of circumferentially spaced spokes which centrally support the hub on the rim; a wheel decorating ornament comprising an annular, planar sheet of material decorated on opposite sides, axially disposed between the groups of spokes and radially disposed between the rim and the hub.
1,093Â citations
TL;DR: The FAN (fan-out-oriented test generation algorithm) is presented, which is faster and more efficient than the PODEM algorithm reported by Goel and an automatic test generation system composed of the FAN algorithm and the concurrent fault simulation.
Abstract: In order to accelerate an algorithm for test generation, it is necessary to reduce the number of backtracks in the algorithm and to shorten the process time between backtracks. In this paper, we consider several techniques to accelerate test generation and present a new test generation algorithm called FAN (fan-out-oriented test generation algorithm). It is shown that the FAN algorithm is faster and more efficient than the PODEM algorithm reported by Goel. We also present an automatic test generation system composed of the FAN algorithm and the concurrent fault simulation. Experimental results on large combinational circuits of up to 3000 gates demonstrate that the system performs test generation very fast and effectively.
821Â citations
TL;DR: The author describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits, which allows for the addition of heuristics used by structural search methods, and has produced excellent results on popular test pattern generation benchmarks.
Abstract: The author describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: first, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits, and second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from previous methods now in use, which search the circuit structure directly instead of constructing a formula from it. The new method is general and effective. It allows for the addition of heuristics used by structural search methods, and it has produced excellent results on popular test pattern generation benchmarks. >
704Â citations
25 Feb 1991
TL;DR: HITEC is presented, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state, and several new techniques are introduced to improve the performance of test generation.
Abstract: This paper presents HITEC, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state Several new techniques are introduced to improve the performance of test generation A targeted D element technique is presented, which greatly increases the number of possible mandatory assignments and reduces the over-specification of state variables which can sometimes result when using a standard PODEM algorithm A technique to use the state knowledge of previously generated vectors for state justification, without the memory overhead of a state transition diagram is presented For faults that were aborted during the standard test generation phase, knowledge that was gained about fault propagation, by the fault simulator, is used These techniques, when used together, produce the best published results for the ISCAS89 sequential benchmark circuits
673Â citations
References
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01 Jan 1972
TL;DR: The principles of integer programming are directed toward finding solutions to problems from the fields of economic planning, engineering design, and combinatorial optimization as mentioned in this paper, which is a standard of graduate-level courses since 1972.
Abstract: The principles of integer programming are directed toward finding solutions to problems from the fields of economic planning, engineering design, and combinatorial optimization. This highly respected and much-cited text, a standard of graduate-level courses since 1972, presents a comprehensive treatment of the first two decades of research on integer programming.
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TL;DR: The essential features of the branch-and-bound approach to constrained optimization are described, and several specific applications are reviewed, including integer linear programming Land-Doig and Balas methods, nonlinear programming minimization of nonconvex objective functions, and the quadratic assignment problem Gilmore and Lawler methods.
Abstract: The essential features of the branch-and-bound approach to constrained optimization are described, and several specific applications are reviewed. These include integer linear programming Land-Doig and Balas methods, nonlinear programming minimization of nonconvex objective functions, the traveling-salesman problem Eastman and Little, et al. methods, and the quadratic assignment problem Gilmore and Lawler methods. Computational considerations, including trade-offs between length of computation and storage requirements, are discussed and a comparison with dynamic programming is made. Various applications outside the domain of mathematical programming are also mentioned.
1,915Â citations
"An Implicit Enumeration Algorithm t..." refers methods in this paper
...The integer programming problem and various problems in the field of artifical intelligence have been approached using state space search methods [5] and the branch and bound technique [6] haustively, examined as tests for a given fault....
[...]
Book•
01 Jan 1971
TL;DR: This paper will concern you to try reading problem solving methods in artificial intelligence as one of the reading material to finish quickly.
Abstract: Feel lonely? What about reading books? Book is one of the greatest friends to accompany while in your lonely time. When you have no friends and activities somewhere and sometimes, reading book can be a great choice. This is not only for spending the time, it will increase the knowledge. Of course the b=benefits to take will relate to what kind of book that you are reading. And now, we will concern you to try reading problem solving methods in artificial intelligence as one of the reading material to finish quickly.
1,431Â citations
"An Implicit Enumeration Algorithm t..." refers methods in this paper
...The integer programming problem and various problems in the field of artifical intelligence have been approached using state space search methods [5] and the branch and bound technique [6] haustively, examined as tests for a given fault....
[...]
TL;DR: The problem considered is the diagnosis of failures of automata, specifically, failures that manifest themselves as logical malfunctions, and an algorithm is developed which utilizes this calculus to compute tests to detect failures.
Abstract: The problem considered is the diagnosis of failures of automata, specifically, failures that manifest themselves as logical malfunctions. A review of previous methods and results is first given. A method termed the "calculus of D-cubes" is then introduced, which allows one to describe and compute the behavior of failing acyclic automata, both internally and externally. An algorithm, called the D-algorithm, is then developed which utilizes this calculus to compute tests to detect failures. First a manual method is presented, by means of an example. Thence, the D-algorithm is precisely described by means of a program written in Iverson notation. Finally, it is shown for the acyclic case in which the automaton is constructed from AND'S, NAND'S, OR'S and NOR'S that if a test exists, the D-algorithm will compute such a test.
869Â citations
IBM1
TL;DR: A logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI is described, based on two concepts that are nearly independent but combine efficiently and effectively.
Abstract: The ability to put hundreds of logic gates on a single chip of silicon offers great potential for reducing power, increasing speed, and reducing cost. Unfortunately, several problems must be solved in order to exploit these advantages of large-scale integration, LSI. This paper will describe a logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI. The design method is based on two concepts that are nearly independent but combine efficiently and effectively. The first is to design sequential logic structures so that correct operation is not dependent on signal rise and fall time or on circuit or wire delay. The second is to design all the internal storage elements (other than memory arrays) so that they can also be operated as shift registers to facilitate testing and diagnostics. Sequential logic, which is difficult to test, can then be transformed to combinational logic, which is less difficult. The transformation is performed during test generation. Advantages and cost impact will also be discussed qualitatively.
861Â citations