An Improved Quasi-Saturation and Charge Model for SOI-LDMOS Transistors
TL;DR: In this article, an accurate quasi-saturation model and a nodal charge model for silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (SOI-LDMOS) transistors are presented.
Abstract: In this paper, we report an accurate quasi-saturation model and a nodal charge model for silicon-on-insulator lateral double-diffused metal–oxide–semiconductor (SOI-LDMOS) transistors. First, a model of a 2-D SOI resistor under velocity saturation is developed, which is subsequently incorporated into the drift region of an LDMOS transistor to predict the quasi-saturation effect. The gate-voltage dependence of the quasi-saturation current is also modeled. Second, we propose a new nodal charge model to describe the dynamic behavior of the device. Comparisons of modeling results with device simulation data show that the proposed model is accurate over a wide range of bias. Scalability of the model with respect to the length of the drift region under the field oxide is also demonstrated. Finally, the model is validated under device self-heating conditions and by comparing it with the experimental data.
Citations
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01 Jan 2006
TL;DR: In this paper, the surface potential-based compact transistor model, MOS Model 20 (MM20), has been extended with a quasi-saturation, an effect that is typical for LDMOS devices with a long drift region.
Abstract: The surface-potential-based compact transistor model, MOS Model 20 (MM20), has been extended with a quasi-saturation, an effect that is typical for LDMOS devices with a long drift region As a result, MM20 extends its application range from low-voltage LDMOS devices up to high-voltage LDMOS devices of about 100V In this paper, the new dc model of MM20, including quasi-saturation, is presented The addition of velocity saturation in the drift region ensures the current to be controlled by either the channel region or the drift region A comparison with dc measurements on a 60-V LDMOS device shows that the new model provides an accurate description in all regimes of operation, ranging from subthreshold to superthreshold, in both the linear and saturation regime Thus, owing to the inclusion of quasi-saturation also the regime of high-gate and high-drain bias conditions for high-voltage LDMOS devices is accurately described
70 citations
TL;DR: In this article, a 3D analytical model for the SOI LDMOS with alternating silicon and high-k dielectric pillars (HKLDMOS) is presented.
11 citations
01 Jan 2010
TL;DR: MOS Model 20 as mentioned in this paper is an advanced public-domain compact LDMOS model, to be used for circuit simulation of high-voltage IC-designs, which includes all specific highvoltage aspects into one model.
Abstract: MOS Model 20 is an advanced public-domain compact LDMOS model, to be used for circuit simulation of high-voltage IC-designs. By combining the description of the MOSFET channel region with that for the drift region of an LDMOS device, MOS Model 20 includes all specific high-voltage aspects into one model. This chapter presents the physical background of the model, the model parameter extraction strategy, and ends with the verification in comparison to dc- and ac-measurements.
2 citations
01 Dec 2016
TL;DR: In this paper, a power amplifier is designed both within the TCAD mixed-mode simulation framework and circuit simulator using the Verilog-A compact model, which can accurately predict the existence of double IMD sweetspots for class AB operation.
Abstract: In this paper, intermodulation distortion (IMD) analysis is carried out for silicon-on-insulator lateral double-diffused metal-oxide-semiconductor using a physics-based large signal model implemented in Verilog-A. The model is found to predict the static and dynamic characteristics accurately along with the higher order derivatives of transconductance and capacitances in all regions of operations. A power amplifier (PA) is designed both within the TCAD mixed-mode simulation framework and circuit simulator using the Verilog-A compact model. One-tone and two-tone analysis are carried out for the PAs designed in TCAD and circuit simulators. It is found that the Verilog-A compact model can accurately predict the existence of double IMD sweetspots for class AB operation when compared with the TCAD results. Also for the output power, power gain and power added efficiency, the model predictions are in agreement with those of the TCAD simulation data.
1 citations
Cites background or methods from "An Improved Quasi-Saturation and Ch..."
...1 is added along with the main large signal model to take care of the self heating effects [7][8]....
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...The SOI-LDMOS structure reported in [8] is used for carrying out the simulations using the commercially available device simulator, MEDICI (TCAD) [11]....
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...LDMOS transistors using the model of [8] implemented in Verilog-A....
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...Subsequent work on the dynamic large-signal modeling is reported in [8]....
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...The equivalent circuit model of SOI-LDMOS transistor reported in [8] is shown in Fig....
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TL;DR: In this paper, the effect of charge partitioning in a silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor on its nonlinearity model is investigated.
Abstract: In this article, the effect of charge partitioning in a silicon-on-insulator lateral double-diffused metal–oxide–semiconductor (LDMOS) transistor on its nonlinearity model is investigated. It is found that the prediction of the third-order intermodulation distortion (IM3) depends on the model equivalent circuit (EC) and appropriate charge assignments at various nodes therein. The investigation is carried out using a highly accurate static model of LDMOS along with a couple of different charge-partitioning schemes in order to single out their effects on the nonlinearity model behavior. We observe that charge partitioning in a more flexible EC framework yields an improved IM3 prediction when compared with the TCAD simulated results.
1 citations
Cites background or methods from "An Improved Quasi-Saturation and Ch..."
...the model derivation can be found in [11] and [12]....
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...The charge model reported in [12] assigns the charges to five nodes (i....
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...Large-signal model for the SOI-LDMOS transistor [12]....
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...In this article, first, we present that our physics-based compact model reported in [11] and [12] is capable of accurately...
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...A physics-based static compact model for a silicon-on-insulator (SOI) LDMOS transistor is reported in [11], which is subsequently improved in [12] to include the dynamic large-signal behavior....
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References
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01 Dec 1967
TL;DR: In this article, the experimental dependence of carrier mobilities on doping density and field strength in silicon has been investigated and the curve-fitting procedures are described, which fit the experimental data.
Abstract: Equations are presented which fit the experimental dependence of carrier mobilities on doping density and field strength in silicon. The curve-fitting procedures are described.
1,539 citations
"An Improved Quasi-Saturation and Ch..." refers methods in this paper
...where Eeff is the average electric field in the resistor, EC = vsat/μdr1 is the critical electric field, q is the electronic charge, Ndr1 is the doping concentration, tsi, W, and LLC are the thickness, width, and length of the resistor, respectively, μdr1 is the low field mobility, vsat is the saturation velocity, θdr1 is a model parameter which is used to obtain a smooth transition into the velocity saturation regime, Vdd′ is the voltage applied across the resistor, and a small positive hyperbolic smoothing parameter δdr1 is added to [15] to ensure continuous differentiability [16]....
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...Using a conventional velocity saturation model [15], the current I flowing through a 1-D semiconductor block is...
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TL;DR: A new model for computer simulation of capacitance effects in MOS transistors is presented, which guarantees conservation of charge and includes bulk capacitances.
Abstract: A new model for computer simulation of capacitance effects in MOS transistors is presented. Transient currents are found directly from the charge distribution in the device rather than from capacitances. The effective capacitances which result are nonreciprocal. The model guarantees conservation of charge and includes bulk capacitances. Several circuit examples are considered.
395 citations
"An Improved Quasi-Saturation and Ch..." refers background in this paper
...This is because the conventional WD [17], [18] charge partitioning to various nodes cannot be applied....
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TL;DR: In this paper, two methods have been developed for analyzing MOS transients: analytical and quasi-static approximation, and numerical and a new boundary value method which can be applied over a wide range of operating speeds.
Abstract: Two methods have been developed for analyzing MOS transients. One method is analytical and uses the quasi-static approximation. It is useful when the stray capacitance dominates MOS transient performance. The second method is numerical and uses a new boundary value method which can be applied over a wide range of operating speeds. This method includes secondary effects and nonuniform doping, The validity and limits for both methods are verified by comparison with measurements. Transit-time delay and charge-pumping effects are also analyzed using the numerical method. Examples of short-channel behavior of MOS devices are included.
125 citations
"An Improved Quasi-Saturation and Ch..." refers background in this paper
...This is because the conventional WD [17], [18] charge partitioning to various nodes cannot be applied....
[...]
21 Oct 2004
TL;DR: This work provides a quick introduction to writing compact models in Verilog-A and, by indicating the sorts of techniques that compact model writers may use, helps simulator vendors understand the sort of optimizations that are expected from their Verilogy-A interfaces.
Abstract: Verilog-A was recently enhanced to provide greater support for compact modeling In order for Verilog-A to become the standard language for compact model development and implementation, two more steps are necessary: compact model developers must become familiar with the language, and simulators must run compact models written in Verilog-A almost as quickly and reliably as those hand-coded in C This work addresses both of these steps: it provides a quick introduction to writing compact models in Verilog-A and, by indicating the sorts of techniques that compact model writers may use, helps simulator vendors understand the sorts of optimizations that are expected from their Verilog-A interfaces
115 citations
"An Improved Quasi-Saturation and Ch..." refers methods in this paper
...A successful implementation of the model is carried out in Verilog-A....
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...The proposed model is implemented in Verilog-A [23] and simulated using Spectre [24]....
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TL;DR: In this article, the surface potential-based compact transistor model, MOS Model 20 (MM20), has been extended with a quasi-saturation, an effect that is typical for LDMOS devices with a long drift region.
Abstract: The surface-potential-based compact transistor model, MOS Model 20 (MM20), has been extended with a quasi-saturation, an effect that is typical for LDMOS devices with a long drift region. As a result, MM20 extends its application range from low-voltage LDMOS devices up to high-voltage LDMOS devices of about 100V. In this paper, the new dc model of MM20, including quasi-saturation, is presented. The addition of velocity saturation in the drift region ensures the current to be controlled by either the channel region or the drift region. A comparison with dc measurements on a 60-V LDMOS device shows that the new model provides an accurate description in all regimes of operation, ranging from subthreshold to superthreshold, in both the linear and saturation regime. Thus, owing to the inclusion of quasi-saturation also the regime of high-gate and high-drain bias conditions for high-voltage LDMOS devices is accurately described.
76 citations