An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II (Two-Dimensional Study-Biasing & Comparison With NMOS)
TL;DR: In this paper, the impact of both substrate and gate bias on the regenerative avalanche injection phenomenon at the edge of drain contact was analyzed for drain extended n-channel metaloxide-semiconductor (DeNMOS).
Abstract: In this paper, we present an analysis of drain extended n-channel metal-oxide-semiconductor (DeNMOS) and study the impact of both substrate and gate biasing on the regenerative avalanche injection phenomenon at the edge of drain contact. We will demonstrate that the flow and distribution of avalanche-generated holes and electrons are significantly impacted by biasing the gate and pumping current through the substrate. Finally, we show that gate bias or drain bias, when individually applied, can only lead to marginal improvement in It2; however, when both the biases are applied simultaneously, it can then optimally improve the failure performance. Subsequently, we compare high current performance of DeNMOS with NMOS or swapped DeNMOS configuration through a simplified 1-D macroscopic model.
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TL;DR: In this article, the limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes.
Abstract: This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.
72 citations
Cites background from "An Insight Into ESD Behavior of Nan..."
...6(b)] oxide isolation in the drift region [12]–[15]....
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TL;DR: In this paper, the scope of drain-extended FinFET (DeFinFET) as a highvoltage (HV) device contender for Fin-based SoC applications is explored.
Abstract: This article explores the scope of drain-extended FinFET (DeFinFET) as a high-voltage (HV) device contender for Fin-based SoC applications. For the first time, guidelines for efficient and reliable HV integration in sub-14 nm FinFET nodes are given. Up to what extent DeFinFET stands as a promising choice is carefully investigated through device-circuit interactions and reliability analysis of range of DeFinFET options. The same is then compared, in terms of radio frequency (RF)-power amplifier (PA) performance, dc–dc conversion efficiency, electrostatic discharge (ESD) robustness, and hot carrier immunity (HCI) reliability, with other HV alternatives in FinFET nodes and its planar counterpart, that is drain-extended MOS (DeMOS).
5 citations
Cites methods from "An Insight Into ESD Behavior of Nan..."
...For this work, a well-calibrated 3-D process and device simulation setup was used, as reported in our earlier work [17]....
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TL;DR: In this paper, single and multi-Fin behavior of drain-extended FinFET (DeFinFET) devices under low and high current injection conditions is studied using detailed 3-D TCAD simulations.
Abstract: Single and multi-Fin behavior of drain-extended FinFET (DeFinFET) devices under low and high current injection conditions is studied using detailed 3-D TCAD simulations. For completeness, electrostatic discharge (ESD) behavior of both shallow trench isolation (STI)-type and non-STI-type DeFinFET devices is studied. Under low current injection, junction breakdown, parasitic bipolar turn-on, as well as the onset of space charge modulation and its implications on high current behavior are explored. Under high current injection, the role of space charge modulation in electrothermal instability and filament formation is discussed. Unique filament spreading behavior has been discovered in DeFinFETs. Fin-based construction was found responsible for filament spreading. The interplay among bipolar turn-on, bipolar efficiency, filament density, and nature of filament spreading is explained.
2 citations
Cites result from "An Insight Into ESD Behavior of Nan..."
...Although several works have reported the ESD failure mechanism of planar DeMOS or laterally double diffused MOS (LDMOS) devices [6]–[10], similar work on DeFinFET is broadly missing except a preliminary work by Sampath Kumar et al....
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TL;DR: In this paper, the performance of drain-extended NMOS (DeNMOS) under 28 and 40-nm bulk CMOS process is investigated. But, the performance is limited by the complexity of the DeMOS-SCR.
Abstract: Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.
1 citations
DOI•
TL;DR: In this article , physical insights on drain extended NMOS (DeNMOS) transient switching reliability under unclamped inductive load (UIL) conditions were presented, where increased body contact length of the proposed DeNMOS offers the dual benefit of P-BJT mitigation and delayed SCM without degrading the DC electrical performance.
Abstract: This work presents physical insights on drain extended NMOS (DeNMOS) transient switching reliability under unclamped inductive load (UIL) conditions. The dependence of UIL switching dynamics on the rate of carrier injection after parasitic bipolar junction transistor (P-BJT) triggering and subsequent space charge modulation (SCM) is demonstrated using a 2D TCAD simulation study. In DeNMOS, reduced body resistance suppresses the P-BJT while increasing the back gate bias delays the SCM. We show that the increased body contact length of the proposed DeNMOS offers the dual benefit of P-BJT mitigation and delayed SCM without degrading the DC electrical performance. Furthermore, it is shown that mitigation of P-BJT and delayed SCM enhance the turn-off reliability against thermal runaway when DeNMOS is subjected to transient switching conditions in the presence of UIL. Finally, we show that when external body resistance and bias are individually applied, they result in limited improvement in switching reliability, whereas body layout engineering could achieve optimum switching reliability. Subsequently, a comparative investigation of the body, drain and drift layout optimization techniques shows the highest enhancement in avalanche ruggedness and robustness against thermal runaway for body contact optimized DeNMOS.
1 citations
References
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TL;DR: In this article, the authors present the results of an extensive experimental program to determine pulse power failure levels of semiconductor junctions, and a semi-empirical formula, based on experimental data and on a simple thermal failure model is given.
Abstract: Theoretical predictions of circuit failure in an Electromagnetic Pulse (EMP) environment require a knowledge of failure levels for each component of the circuit due to surge voltages or currents. For most circuits, the semiconductor devices are the weakest elements with respect to such failure. This paper presents the results of an extensive experimental program to determine pulse power failure levels of semiconductor junctions. Approximately 80 different types of silicon diodes and transistors were studied with variations in junction areas from 10-4to 10-1 cm2 and with widely varying junction geometries. Power levels of up to two kilowatts, with time durations of 0.1 to 20 microseconds, were applied to semiconductor junctions in both forward and reverse polarity modes. A semi-empirical formula, based on experimental data and on a simple thermal failure model is given. From the formula one can make order-of-magnitude estimates of the failure level as a function of pulse length for many silicon diodes or transistors whose junction area is known.
376 citations
TL;DR: In this paper, it was shown that all germanium junctions break down as the result of the same avalanche process found in silicon, and an empirical expression for the multiplication inherent in this breakdown process was given for step junctions.
Abstract: It is shown that all germanium junctions studied break down as the result of the same avalanche process found in silicon. An empirical expression for the multiplication inherent in this breakdown process is given for step junctions. Ionization rates for holes and electrons in Ge are derived with the use of this expression. The ionization rate for holes is larger than that for electrons by about a factor of two. The agreement between these ionization rates as a function of field and the theory of Wolff is excellent. It is determined that the threshold for electron-hole pair production is about 1.50 ev and the mean free path for electron (or hole)-phonon collisions is about 130 A.
320 citations
"An Insight Into ESD Behavior of Nan..." refers background in this paper
...Therefore, the classical Miller formulation [23] is modified by a term comprising electron current density under the currentcontrolled model (Table II)....
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TL;DR: In this paper, it was shown that transistors having thin, lightly doped collector regions are particularly susceptible to avalanche injection, which suggests that some compromise may be necessary in the design of high-frequency power transistors.
Abstract: A rapid type of second breakdown observed in silicon n+-p-n-n+transistors is shown to be due to avalanche injection at the collector n-n+junction. Localized thermal effects, which are usually associated With second breakdown, are shown to play a minor role in the initiation of the transition to the low voltage state. A useful tool in the analysis of avalanche injection is the n+-n-n+diode, which exhibits negative resistance at a critical voltage and current. A close correspondence between the behavior of the diode and the transistor (open base) is established both theoretically and experimentally. Qualitative agreement with the proposed model is obtained for both directions of base current flow. It is shown that transistors having thin, lightly doped collector regions are particularly susceptible to avalanche injection, which suggests that some compromise may be necessary in the design of high-frequency power transistors.
214 citations
TL;DR: In this paper, a first principles approach to the problem of thermal breakdown in semiconductor devices is developed using Green's function formalism, which allows all three dimensions of the defect to take on the full range of values.
Abstract: A first principles approach to the problem of thermal breakdown in semiconductor devices is developed using Green's function formalism. The problem of thermal runaway at a defect of arbitrary geometry, subject to an arbitrary power profile, is considered. A solution is presented for the specific case of a rectangular parallelepiped shaped defect, subject to constant input power. It is expected that this geometry will model the defect in many semiconductor devices more accurately than the defect geometries used in the past. Unlike previous work, this allows all three dimensions of the defect to take on the full range of values. The theory developed here provides a natural framework for the explanation of results previously reported in the literature. It is shown that there are four time domains and not three as previously thought, and these exist for all shapes of defect. Thus, it is wrong to conclude that a pulse power/time to failure dependence of the form P f α t f − 1 2 necessarily implies a roughly two-dimensional defect. Several relationships are found to exist within the model which allow estimates to be made of the defect dimensions and failure temperature. Experimental data drawn from the literature, produce Pf/tf profiles similar to those indicated by the theory.
206 citations
TL;DR: In this article, a 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes has been reported, with a double RESURF technique in conjunction with a deep drain engineered profile that eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation.
Abstract: This letter reports a novel 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes. This device features a double RESURF technique in conjunction with a deep drain engineered profile that eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation. Maximum second breakdown current (I/sub t2/) of 16 mA//spl mu/m has been realized in a 100 ns transmission line pulse (TLP) measurement even with a higher holding voltage of 20 V. ESD protection level in excess of 5 kV with an equivalent human body model (HBM) has been shown to be feasible for this device without significant compromise in device size.
64 citations
"An Insight Into ESD Behavior of Nan..." refers background in this paper
...As the bipolar turns on fully, the electron and hole path critically influence the process of localization in both DeNMOS and regular NMOS first in the 2-D plane [14]–[20]....
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