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An Insight Into Self-Heating Effects and Its Implications on Hot Carrier Degradation for Silicon-Nanotube-Based Double Gate-All-Around (DGAA) MOSFETs

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TLDR
In this article, 3-dimensional (3-D) electrothermal simulations using coupled hydrodynamic and thermodynamic transport models are performed to analyze the electrothermodynamic behavior and self-heating effects in ultra-thin DGAA MOSFETs.
Abstract
Silicon-Nanotube-based ultra-thin DGAA MOSFETs have been extensively studied for their superior immunity to short channel effects (SCEs) and better drive current capability; however, the reliability issues owing to self-heating effects (SHEs) and hot carrier injection (HCI) degradation are yet to be investigated systematically. In advanced non-planar device structures, an increase in power density due to ultra-scaled device dimensions can aggravate both the carrier heating as well as lattice heating. In this paper, 3-dimensional (3-D) electrothermal (ET) simulations using coupled hydrodynamic and thermodynamic transport models are performed to analyze the electrothermal behavior and SHEs in ultra-thin DGAA MOSFET. 3-D TCAD simulation parameters are calibrated with the data obtained from the literature. Through advanced 3-D ET simulations, we demonstrate that the device thermal contact resistance adversely influences both the carrier temperature as well as lattice temperature. The implication of SHE on the device output drive current reduction is also analyzed. The effective drive current method is used to observe the impact of SHE on the intrinsic delay of the device. Further, the performance of the device due to HCI is also highlighted. HCI significantly degrades the overall device performance leading to increased gate leakage current. Finally, the reliability issues induced by SHEs with on-chip ambient temperature variations have also been interpreted using Sentauras based TCAD simulator.

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Journal ArticleDOI

Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET

TL;DR: In this paper , the authors investigated the impact of ambient temperature and interface thermal contact resistance induced self heating effect in the stacked nanosheet field effect transistors (NS-FET) using extensive numerical simulations.
Posted ContentDOI

Investigating the Impact of Self-Heating Effects on Some Thermal and Electrical Characteristics of Dielectric Pocket Gate-All-Around (DPGAA) MOSFETs

TL;DR: In this article, a comprehensive investigation under the influence of self-heating effects has been done for the variation in the lattice and carrier temperature against spacer length, ambient temperature, device length, and thermal contact resistance including ON and Off currents with gate bias voltage (VGS).
Journal ArticleDOI

Physical Insight into Self-heating Induced Performance Degradation in RingFET

TL;DR: In this paper, an investigation on the electro-thermal (ET) behavior of the nanoscale RingFET has been conducted using the Sentaurus TCAD device simulator.
References
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TL;DR: In this paper, the Golden Rule is applied to properties of quantum wells and the properties of GaAs-AlAs alloys at room temperature and the Hermite's equation: harmonic oscillator.
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Multiple-gate SOI MOSFETs

TL;DR: In this paper, the authors describe the evolution and properties of a new class of MOSFETs, called triple-plus (3 + )-gate devices, which offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOS-FET.
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Nanowire Transistor Performance Limits and Applications

TL;DR: In this paper, the authors review advances in chemically synthesized semiconductor nanowires as nanoelectronic devices and discuss 3-D heterogeneous integration that is uniquely enabled by multifunctional nanowire within a bottom-up approach.
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The effective drive current in CMOS inverters

TL;DR: This definition of I/sub eff/ accurately captures the delay behavior of non-traditionally scaled devices, where mobility and V/sub T//V/sub dd/ are scaled in neither a regular nor uniform manner.
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