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Journal ArticleDOI

An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device—Part I: Turn-On Behavior of the Parasitic Bipolar

TL;DR: In this paper, the authors present experiments and models to understand the physics of bipolar turn-on and its impact on the onset of space-charge modulation in a drain-extended n-type metaloxide-semiconductor (DENMOS) device.
Abstract: A second-breakdown phenomenon (It2) in a drain-extended n-type metal-oxide-semiconductor (DENMOS) is associated with complex triggering of a parasitic bipolar transistor. Full comprehension of the problem requires 3-D modeling; however, there is even deficiency in the understanding of the phenomenon occurring in the 2-D cross-sectional plane. We present experiments and models to understand the physics of bipolar turn-on and its impact on the onset of space-charge modulation in a DENMOS device. We present a detailed analysis of the current paths involved during the bipolar turn-on. We show that a strong snapback is triggered due to coupling of the parasitic bipolar turn-on in a deeper region of the p-body and avalanche injection at the drain junction. Furthermore, we show that the ballast resistor formed in the drain region due to current crowding of electrons under high-current conditions can be modeled through a simplified 1-D analysis of the n+/n- resistive structure.
Citations
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Journal ArticleDOI
TL;DR: In this article, the limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes.
Abstract: This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.

72 citations

Journal ArticleDOI
Jie Zeng1, Shurong Dong1, J.J. Liou1, Yan Han1, Lei Zhong1, Weihuai Wang1 
TL;DR: In this paper, a novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed.
Abstract: A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed in this paper. With a distinguished feature of an imbedded floating P+ region, the GGISCR is demonstrated to be superior to the conventional low voltage triggered SCR and GGnMOS in terms of high area efficiency and high holding voltage. The operational mechanism of GGISCR device is discussed in detail, and the effect of floating P+ region on the GGISCR’s $I$ – $V$ characteristics is analyzed via TCAD simulation results as well.

24 citations


Cites background from "An Insight Into the ESD Behavior of..."

  • ...As such a large ESD current goes through the Rn-well resistance, the space charge limited (SCL) transportation occurs in the N-well region [17]–[19], which causes a high electric field and significant impact ionization....

    [...]

Journal ArticleDOI
TL;DR: In this article, a new nanocrystal quantum-dot (NC-QD)-based tunable on-chip electrostatic discharge (ESD) protection mechanism and structures are presented.
Abstract: This paper reports a new nanocrystal quantum-dot (NC-QD)-based tunable on-chip electrostatic discharge (ESD) protection mechanism and structures. Experiments validated the programmable ESD protection concept. Prototype structures achieved an adjustable ESD triggering voltage range of 2.5 V, very fast response to ESD transients of rising time tr ~ 100 ps and pulse duration td; ~ ns, ESD protection density of 25 mA/μm in human body model and 400 mA/μm in charged device model equivalent stressing, and a very low leakage current of Ileak ~ 15 pA. The NC-QD ESD protection concept can potentially be used to design field-programmable on-chip ESD protection circuitry for mixed-signal ICs in nanoscales.

20 citations

Proceedings ArticleDOI
01 Jan 2011
TL;DR: In this article, an unexpected gate oxide failure has been observed during HBM ESD stress on high-voltage tolerant nLDMOS-SCR devices in standard lowvoltage CMOS technology.
Abstract: Unexpected gate oxide failure has been observed during HBM ESD stress on high-voltage tolerant nLDMOS-SCR devices in standard low-voltage CMOS technology. TCAD simulations show that this early gate-oxide failure is due to high current injection originating from the additional discharge current of the inherent HBM board capacitance.

11 citations

Journal ArticleDOI
Jie Zeng1, Shurong Dong1, Lei Zhong1, Guo Wei1, Yan Han1, Weicheng Liu1, Hongwei Li, Jun Wang 
TL;DR: The proposed FP-LDMOS-SCR, same driver capability with LDMOS, can be applied in HV output circuit and also provide its ESD self-protection through shunted ESD stress to ground and the results of Technology Computer Aided Design simulations will be presented.

6 citations


Cites background from "An Insight Into the ESD Behavior of..."

  • ...Among These discussed electric effects which make the normal nLDMOS shows early thermal failure [10,11], the impact ionization generated hole is the fundamental fact....

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References
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Book
01 Jan 1970

3,145 citations

Journal ArticleDOI
TL;DR: In this paper, it was shown that transistors having thin, lightly doped collector regions are particularly susceptible to avalanche injection, which suggests that some compromise may be necessary in the design of high-frequency power transistors.
Abstract: A rapid type of second breakdown observed in silicon n+-p-n-n+transistors is shown to be due to avalanche injection at the collector n-n+junction. Localized thermal effects, which are usually associated With second breakdown, are shown to play a minor role in the initiation of the transition to the low voltage state. A useful tool in the analysis of avalanche injection is the n+-n-n+diode, which exhibits negative resistance at a critical voltage and current. A close correspondence between the behavior of the diode and the transistor (open base) is established both theoretically and experimentally. Qualitative agreement with the proposed model is obtained for both directions of base current flow. It is shown that transistors having thin, lightly doped collector regions are particularly susceptible to avalanche injection, which suggests that some compromise may be necessary in the design of high-frequency power transistors.

214 citations

Journal ArticleDOI
TL;DR: In this paper, the physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated in detail by transmission line pulse (TLP) measurements, human body model (HBM) testing, emission microscopy (EMMI) experiments, and two-dimensional (2-D) device simulations.
Abstract: The physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated in detail by transmission line pulse (TLP) measurements, human body model (HBM) testing, emission microscopy (EMMI) experiments, and two-dimensional (2-D) device simulations. Inhomogeneous triggering caused by device topology as well as the sustained nonhomogeneous current flow due to the unusual electrical behavior are accurately analyzed in single- and multi-finger devices.

118 citations


"An Insight Into the ESD Behavior of..." refers background in this paper

  • ...The weak behavior of the DENMOS is explained through inhomogeneous triggering of bipolars along the width as it leads to current filamentation due to localized heating and permanent damage of the device [2], [5]–[6]....

    [...]

Journal ArticleDOI
V. Parthasarathy1, Vishnu K. Khemka1, Ronghua Zhu1, J. Whitfield1, Amitava Bose1, R. Ida1 
TL;DR: In this article, a 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes has been reported, with a double RESURF technique in conjunction with a deep drain engineered profile that eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation.
Abstract: This letter reports a novel 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes. This device features a double RESURF technique in conjunction with a deep drain engineered profile that eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation. Maximum second breakdown current (I/sub t2/) of 16 mA//spl mu/m has been realized in a 100 ns transmission line pulse (TLP) measurement even with a higher holding voltage of 20 V. ESD protection level in excess of 5 kV with an equivalent human body model (HBM) has been shown to be feasible for this device without significant compromise in device size.

64 citations

Proceedings ArticleDOI
22 May 2000
TL;DR: In this article, a novel lateral power device structure with a very high degree of ESD (electrostatic discharge) robustness is presented, called SCR-LDMOS, which is a modification of the lateral LDMOSFET with good on state and blocking characteristics.
Abstract: A novel lateral power device structure with a very high degree of ESD (electrostatic discharge) robustness is presented This device called the SCR-LDMOS is a modification of the lateral LDMOSFET with good on state and blocking characteristics

57 citations