An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies
01 Apr 2007-pp 608-609
TL;DR: In this article, the second breakdown phenomenon (It2) in drain extended NMOS (DENMOS) which is associated with complex triggering of the parasitic BJT is relatively less understood.
Abstract: Second breakdown phenomenon (It2) in drain extended NMOS (DENMOS) which is associated with complex triggering of the parasitic BJT is relatively less understood. We present experiments and models to understand the physics of snapback in DENMOS in nanometer scale technologies. Avalanche injection phenomenon at the drain contact has been analyzed for a 90 nm DENMOS transistor under high current stressing
Citations
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TL;DR: In this article, a shallow-trench-isolation (STI)-type drained-enhanced n-channel metal-oxide-semiconductor (DeNMOS) device was proposed to achieve an improvement in failure threshold (IT2) and electrostatic discharge (ESD) window (VT2).
Abstract: Time evolution of self-heating and current filamentation are discussed in this paper for shallow-trench-isolation (STI)-type drained-enhanced n-channel metal-oxide-semiconductor (DeNMOS) devices. A deeper insight toward regenerative n-p-n action and its impact over various phases of filamentation and the final thermal runaway is presented. A modified STI-type DeNMOS device is proposed in order to achieve an improvement (~2×) in the failure threshold (IT2) and electrostatic discharge (ESD) window (VT2). The performance and filament behavior of the standard device under charge-device-model-like ESD conditions is also presented, which is further compared with the proposed modified device.
27 citations
Cites background from "An Insight into the High Current ES..."
...Furthermore, the deep snapback leads to a short circuit power dissipation, which was reported as the dominant cause of second breakdown [6], [7]....
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TL;DR: In this paper, experimental and simulation studies of shallow trench isolation (STI)-type drain-extended n-channel metaloxide-semiconductor devices under human body model (HBM)-like electrostatic discharge (ESD) conditions are given.
Abstract: We present experimental and simulation studies of shallow trench isolation (STI)-type drain-extended n-channel metal-oxide-semiconductor devices under human body model (HBM)-like electrostatic discharge (ESD) conditions. Physical insight toward pulse-to-pulse instability is given. Both the current (ITLP) and time evolution of various events such as junction breakdown, parasitic bipolar triggering, and the base push-out effect are discussed in detail. Differences between the 2-D and 3-D simulation (modeling) approaches are presented, and the importance of 3-D technology-computer-aided-design-based modeling is discussed. Furthermore, a deeper physical insight toward the base push-out is given, which shows significant power dissipation due of space charge build-up, which is found at the onset of self-heating in the 2-D plane.
23 citations
TL;DR: In this paper, a robust FinFET silicon-controlled rectifier (SCR) LDMOS ESD protection device is developed, which replaces the drain contact implant to the P+ implant from N+ implant creates an SCR inside the lDMOS, and when the N+ contact is removed a Schottky SCR is created.
Abstract: A robust FinFET silicon-controlled rectifier (SCR) LDMOS ESD protection device is developed. Replacing the drain contact implant to the P+ implant from N+ implant creates an SCR inside the LDMOS and when the N+ contact is removed a Schottky SCR LDMOS is created. The ESD performance of the baseline FinFET LDMOS is Zero, while that of the SCR LDMOS is 9.2 mA/ $\mu {\mathrm{ m}}$ and Schottky SCR is 4.6 mA/ $\mu \text{m}$ respectively.
15 citations
TL;DR: In this paper, the off-state degradation of n-channel laterally diffused metal-oxide-semiconductor (MOS) silicon-controlled-rectifier electrostatic discharge (ESD) devices for high-voltage applications in standard lowvoltage complementary MOS technology is studied.
Abstract: The OFF-state degradation of n-channel laterally diffused metal-oxide-semiconductor (MOS) silicon-controlled-rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS technology is studied. Based on experimental data and technology computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an n+ poly-Si gate to an n-well is identified to be the driving force of device degradation. Device optimization is proposed, which improves both OFF-state and ESD reliability.
14 citations
02 May 2010
TL;DR: In this article, a 3D device modeling of RESURF or non-STI type DeNMOS device under ESD conditions is presented, where the impact of base push-out, pulse-to-pulse instability and electrical imbalance on the various phases of filamentation is discussed.
Abstract: We present 3D device modeling of RESURF or non-STI type DeNMOS device under ESD conditions. The impact of base push-out, pulse-to-pulse instability and electrical imbalance on the various phases of filamentation is discussed. A new phenomenon called “week NPN action” and the cause of early and fast failure is identified. A modification of the device is proposed which achieved an improvement of ∼5X in failure threshold (I T2 ) and ∼2X in ESD window without degrading its I/O performance.
13 citations
References
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01 Jan 2001
TL;DR: In this paper, the physical mechanisms that influence the triggering and holding voltage in a DMOS transistor in CMOS smart power technology are investigated, and a high and a low holding voltage device can be designed by changing the lateral bipolar base distance and also the trigger voltage can be easily tuned.
Abstract: The physical mechanisms that influence the triggering and holding voltage in a DMOS transistor in CMOS smart power technology are investigated. We demonstrate that a high and a low holding voltage device can be designed by changing the lateral bipolar base distance and that also the trigger voltage can be easily tuned. The layout variation that controls the holding voltage also leads to a different snapback mechanism and a different current flow through the device. Excellent ESD capabilities of 16-20 mA//spl mu/m width have been achieved.
58 citations
TL;DR: In this article, the authors studied the influence of termination layout of the source field on the hot-spot dynamics and discussed conditions for filament motion under non-destructive snap-back conditions, which help homogenize the time averaged current density distribution and enhance the device robustness against electrostatic discharges.
Abstract: Integrated vertical DMOS transistors of a 90-V smart power technology are studied under short-duration current pulses. Movement of current filaments and multiple hot spots observed by transient interferometric mapping under nondestructive snap-back conditions are reported. Device simulations show that the base push-out region associated with the filament can move from cell to cell along the drain buried layer due to the decrease of the avalanche generation rates by increasing temperature. The influence of the termination layout of the source field on the hot-spot dynamics is studied. Conditions for filament motion are discussed. The described mechanisms help homogenizing the time averaged current-density distribution and enhance the device robustness against electrostatic discharges.
46 citations
28 Sep 1999
TL;DR: In this article, the detailed physical mechanisms specific to 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) were investigated by means of TLP measurements/HBM testing, electron emission microscopy (EMMI) measurements, and 2D device simulations.
Abstract: The detailed physical mechanisms specific to 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated by means of TLP measurements/HBM testing, electron emission microscopy (EMMI) measurements, and 2D device simulations. Inhomogeneous triggering caused by device topology as well as the sustained nonhomogenous current flow due to the unusual electrical behaviour are analyzed in single- and multifinger devices. An existing ESD-MOS compact model is extended according to the investigated phenomena. It successfully describes LDMOS high current behaviour.
42 citations
"An Insight into the High Current ES..." refers background in this paper
...While the efficient turn-on behavior of the BJT is utilized for ESD protection in regular low voltage devices, “inefficient” BJT turn-on behavior in the DENMOS causes current in-homogeneity and filamentation resulting in a catastrophic failure of the device [3]-[4]....
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TL;DR: In this paper, the double snapback characteristic in the high-voltage nMOSFET under transmission line pulsing stress was investigated by device simulation and it was found that the holding voltage of the highvoltage NMSFET in snapback breakdown condition is much smaller than the power supply voltage.
Abstract: The double snapback characteristic in the high-voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.
39 citations
11 Sep 2000
TL;DR: In this paper, the authors implemented complementary high-voltage drain extended (DE) MOS transistors into Texas Instruments' state-of-the-art production analog and digital 1.5-1.8 V CMOS technology.
Abstract: Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology (1), (2). These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of , , and plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no cost adder.
29 citations