Proceedings ArticleDOI
An ultra low-power rail-to-rail comparator for ADC designs
Song Lan,Chao Yuan,Yvonne Y. H. Lam,Liter Siek +3 more
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TLDR
In this paper, a novel ultra low-power rail-to-rail comparator is presented, which can be suitably used in low to medium speed A/D converters.Abstract:
This paper presents a novel ultra low-power rail-to-rail comparator which can be suitably used in low-to-medium speed A/D converters. This comparator adopts a preamplifier followed by a dynamic latch structure to achieve fast-decision, high-resolution as well as reduced kick-back noise. A new adaptive power control technique is used to reduce the power consumption of the preamplifier. The circuit is designed and simulated in Global Foundries 65nm CMOS technology. The simulation results have shown that the power consumption of 12-bit comparator is 191.2 nW at the clock frequency of 15 MHz and 0.8 V supply voltage with a delay of 1.17nS.read more
Citations
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Journal ArticleDOI
Design and analysis of an ultra-low-power double-tail latched comparator for biomedical applications
TL;DR: In this paper, a double-tail latched comparator with a self-neutralization technique has been proposed for biomedical applications with a power-delay product of 0.0172 fJ at 100 kHz clock frequency.
Proceedings ArticleDOI
A fully on-chip 25MHz PVT-compensation CMOS Relaxation Oscillator
TL;DR: A fully on-chip, low-power and small area CMOS Relaxation Oscillator (ROSC) with voltage integral feedback structure and a new Bandgap Reference voltage (BGR) for accurate oscillation frequency independent of the PVT and comparator's delay variations is presented.
Journal ArticleDOI
A rail‐to‐rail low‐power latch comparator with time domain bulk‐tuned offset cancellation for low‐voltage applications
Nima Shahpari,Mehdi Habibi +1 more
Journal Article
Implementation of Low Power Rail-To-Rail Dynamic Latch Comparator With Modified Adaptive Power Control Technique
TL;DR: In this article, a modified technique of power reduction for the preamplifier based dynamic latch comparator is presented, which can be used in low-to-medium speed Analog to Digital Converters.
Proceedings ArticleDOI
Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology
TL;DR: Characterization of low operating voltage, high speed and power efficient comparator used as a basic building block in speed optimized Analog to Digital Converters (ADC), such as flash ADC is presented.
References
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Book
CMOS Analog Circuit Design
TL;DR: In this article, the authors present a simple MOS LARGE-SIGNAL MODEL (SPICE Level 1) and a small-signal model for the MOS TRANSISTOR.
Journal ArticleDOI
Kickback noise reduction techniques for CMOS latched comparators
P.M. Figueiredo,J.C. Vital +1 more
TL;DR: This brief reviews existing solutions to minimize the kickback noise and proposes two new ones and HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.
A Low-Offset Double-Tail Latch-Type Voltage Sense Amplifier
TL;DR: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage, which enables fast operation over a wide common-mode and supply voltage range as mentioned in this paper.
Proceedings ArticleDOI
A new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application
TL;DR: A new IV rail-to-rail comparator is presented with low noise, high speed and low power consumption, and a new adaptive power control (APC) technique is proposed to minimize the power dissipation of the comparator.
Proceedings ArticleDOI
A low-kickback-noise latched comparator for high-speed flash analog-to-digital converters
TL;DR: This paper proposes a novel CMOS latched comparator with very low kickback noise for high-speed flash ADCs that separates analog preamplifier from the positive feedback digital dynamic latch so as to reduce the influence of the kick back noise.