An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range
TL;DR: Using a novel self-biasing technique to bias the OTA obviates the need for extra biasing circuitry and enhances the performance and design feasibility under ultra-low-voltage conditions.
Abstract: An operational-transconductance-amplifier (OTA) design for ultra-low voltage ultra-low power applications is proposed. The input stage of the proposed OTA utilizes a bulk-driven pseudo-differential pair to allow minimum supply voltage while achieving a rail-to-rail input range. All the transistors in the proposed OTA operate in the subthreshold region. Using a novel self-biasing technique to bias the OTA obviates the need for extra biasing circuitry and enhances the performance of the OTA. The proposed technique ensures the OTA robustness to process variations and increases design feasibility under ultra-low-voltage conditions. Moreover, the proposed biasing technique significantly improves the common-mode and power-supply rejection of the OTA. To further enhance the bandwidth and allow the use of smaller compensation capacitors, a compensation network based on a damping-factor control circuit is exploited. The OTA is fabricated in a 65 nm CMOS technology. Measurement results show that the OTA provides a low-frequency gain of 46 dB and rail-to-rail input common-mode range with a supply voltage as low as 0.5 V. The dc gain of the OTA is greater than 42 dB for supply voltage as low as 0.35 V. The power dissipation is 182 $\mu{\rm W}$ at $V_{DD}=0.5\ {\rm V}$ and 17 $\mu{\rm W}$ at $V_{DD}=0.35\ {\rm V}$ .
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01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.
1,038 citations
TL;DR: Overall good large-Signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art.
Abstract: A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. The OTA is fabricated in a 180-nm standard CMOS technology, occupies an area of $19.8\cdot 10^{-3}\ \text{mm}^{2}$ and is powered from 0.7 V with a standby current consumption of around 36 $\mu\text{A}$ . DC gain and unity gain frequency are 57 dB and 3 MHz, respectively, under a capacitive load of 20 pF. Overall good large-signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art.
100 citations
Cites result from "An Ultra-Low-Voltage CMOS Process-I..."
...25 times greater than the best result previously reported [23]....
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70 citations
Cites background or methods from "An Ultra-Low-Voltage CMOS Process-I..."
...In recent years, a large number of LV BD OTAs have been reported in the literature.(3-20) Considering these designs, we can conclude that the supply voltage for many truly differential OTAs with a gain‐bandwidth product (GBW) ranging from 1 to 10 MHz is nearly constant and equal to around |VTH| + 0....
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...Lower VDD (close to |VTH|) could be achieved for circuits biased with very low currents (at the cost of a lower GBW),(7,14) or for circuits with pseudo‐differential input stages.(6,16) Therefore, many papers are focused on overcoming the disadvantages of the BD technique rather than further decreasing the supply voltage....
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...Thus, the minimum supply voltage (VDDmin) should be calculated as follows: VDDmin 1⁄4 VGS SS;Tmin;VCMmax ð Þ j j þ VDSsat j j; (16)...
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TL;DR: A simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time.
Abstract: In this article, a new solution for an ultralow-voltage (ULV) ultralow-power (ULP) operational transconductance amplifier (OTA) is presented. Thanks to the combination of a low-voltage bulk-driven nontailed differential stage with the multipath Miller zero compensation technique, a simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time. The proposed OTA was fabricated using the 180-nm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC) and can operate from $V_{\mathbf {DD}}$ ranging from 0.3 to 0.5 V. The 0.3-V version dissipates only 12.6 nW of power while showing a 64.7-dB voltage gain at 1-Hz, 2.96-kHz gain-bandwidth product, and a 4.15-V/ms average slew-rate at 30-pF load capacitance. The measured results agree well with simulations.
53 citations
TL;DR: A new effective single-Miller capacitor compensation topology is introduced for three-stage amplifiers with very large capacitive loads, realized through an active-feedback capacitor together with an inner half-feedforward stage, which profitably exploits the two left half-plane zeros.
Abstract: This paper introduces a new effective single-Miller capacitor compensation topology for three-stage amplifiers with very large capacitive loads, realized through an active-feedback capacitor together with an inner half-feedforward stage. Moreover, an optimized design strategy which profitably exploits the two left half-plane zeros is presented. To improve the amplifier large signal transient response, the topology also includes an external feedforward path, that only marginally affects the frequency compensation, and a novel slew-rate enhancer section. To validate the solutions presented, a three-stage OTA driving a 10-nF load has been designed and implemented in a standard 0.35- $\mu\text{m}$ CMOS technology. The amplifier occupies less than 0.003-mm2 of die area, provides 2.7-MHz gain-bandwidth product and 0.55-V/ $\mu\text{s}$ average slew-rate, while consuming only 25- $\mu\text{A}$ quiescent current.
51 citations
References
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Book•
01 Jan 1999
TL;DR: The analysis and design techniques of CMOS integrated circuits that practicing engineers need to master to succeed can be found in this article, where the authors describe the thought process behind each circuit topology, but also consider the rationale behind each modification.
Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents
1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging
4,826 citations
01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.
1,038 citations
"An Ultra-Low-Voltage CMOS Process-I..." refers background in this paper
...7 illustrates the common-mode half-circuit [18] equivalent representation for this amplifier with and without self-biasing....
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TL;DR: In this paper, a simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications and verified experimentally for both p-and n-channel test transistors of a Si-gate low-voltage CMOS technology.
Abstract: A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (<0.1 /spl mu/W at 32 kHz), and a low-frequency bandpass amplifier. All these circuits are insensitive to threshold and mobility variations, and compatible with a CMOS technology dedicated to digital low-power circuits.
905 citations
"An Ultra-Low-Voltage CMOS Process-I..." refers background in this paper
...The drain current of an MOS transistor in the sub-threshold region [21], [22] is given by...
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TL;DR: In this paper, operational transconductance amplifier (OTA) and filter design for analog circuits with very low supply voltages, down to 0.5 V, are presented. But they do not consider the effect of low-voltage analog circuits on the performance.
Abstract: We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.
471 citations
TL;DR: In this paper, the authors present a 1-V analog op-amp with rail-to-rail input and output ranges, which achieves 1.3 MHz unity gain and 57/spl deg/ phase margin for a 22pF load capacitance.
Abstract: This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal-oxide-semiconductor (CMOS) technology, Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal-oxide-semiconductor field-effect transistor turn-on (threshold) voltage requirement. Finally, techniques are combined within a 1-V CMOS operational amplifier with rail-to-rail input and output ranges. While consuming 300 /spl mu/W, the 1-V rail-to-rail CMOS op amp achieves 1.3-MHz unity-gain frequency and 57/spl deg/ phase margin for a 22-pF load capacitance.
408 citations
"An Ultra-Low-Voltage CMOS Process-I..." refers background in this paper
...Several OTA designs that operate from a supply voltage of 1 V or below have been reported [4]–[15]....
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...This technique circumvents the threshold voltage requirement, thereby extending the allowable operating range [3], [4]....
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