An ultra-low-voltage OTA in 28 nm UTBB FDSOI CMOS using forward body bias
01 Oct 2015-pp 1-4
TL;DR: An ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process that achieves -64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW.
Abstract: This paper presents an ultra-low-voltage, sub-µW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves −64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuous-time common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68°. Sufficient performance is maintained over process, supply voltage and temperature variations.
Citations
More filters
18 Nov 2015
TL;DR: Analog-to-digital converters are crucial blocks which form the interface between the physical world and the digital domain and are indispensable in numerous applications such as wireless telecommunications.
Abstract: Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless s ...
1 citations
TL;DR: Two operational amplifiers designed and fabricated in a 22 nm FD-SOI technology illustrate this technique, as well as its advantages and limitations.
Abstract: Negative feedback applied to the back gate of MOS devices available in FD-SOI (fully depleted silicon on insulator) CMOS technologies can be used to improve the linearity of operational amplifiers. Two operational amplifiers designed and fabricated in a 22 nm FD-SOI technology illustrate this technique, as well as its advantages and limitations.
References
More filters
Book•
01 Jan 1996
TL;DR: In this paper, the authors present an overview of current mirror and Opamp design and compensation for single-stage Amplifiers and Current Mirrors, as well as a comparison of the two types of Opamps.
Abstract: Partial table of contents: Integrated--Circuit Devices and Modelling. Processing and Layout. Basic Current Mirrors and Single--Stage Amplifiers. Noise Analysis and Modelling. Basic Opamp Design and Compensation. Advanced Current Mirrors and Opamps. Comparators. Switched--Capacitor Circuits. Nyquist--Rate D/A Converters. Oversampling Converters. Phase--Locked Loops. Index.
3,118 citations
TL;DR: In this paper, operational transconductance amplifier (OTA) and filter design for analog circuits with very low supply voltages, down to 0.5 V, are presented. But they do not consider the effect of low-voltage analog circuits on the performance.
Abstract: We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.
471 citations
Book•
01 Jan 2012
162 citations
"An ultra-low-voltage OTA in 28 nm U..." refers background in this paper
...However, it is seen that the flicker noise of MOS devices in the 28 nm FDSOI process is considerably higher than that in the 65 nm bulk CMOS process which confirms the general trend that flicker noise worsens with CMOS process scaling [7]....
[...]
...To assess the flicker noise levels of the MOS devices in the FDSOI process, NMOS- and PMOS-input common-source (CS) amplifiers were designed in 28 nm FDSOI and 65 nm bulk CMOS processes....
[...]
...As expected, the NMOS contributes higher flicker noise than the PMOS [7]....
[...]
...For the LVT transistors, the range of FBB voltages is [−0.3 V +3 V] and [−3 V +0.3 V] for the NMOS and PMOS respectively....
[...]
...The bias circuit uses FBB of 2 V and −2 V for the NMOS and PMOS devices respectively and has Ibias = 80 nA....
[...]
TL;DR: A 60-dB gain bulk-driven Miller OTA operating at 0.25-V power supply in the 130-nm digital CMOS process can help overcome some of the constraints imposed by nanometerCMOS process for high performance analog circuits in weak inversion region.
Abstract: This paper presents a 60-dB gain bulk-driven Miller OTA operating at 0.25-V power supply in the 130-nm digital CMOS process. The amplifier operates in the weak-inversion region with input bulk-driven differential pair sporting positive feedback source degeneration for transconductance enhancement. In addition, the distributed layout configuration is used for all the transistors to mitigate the effect of halo implants for higher output impedance. Combining these two approaches, we experimentally demonstrate a high gain of over 60-dB with just 18-nW power consumption from 0.25-V power supply. The use of enhanced bulk-driven differential pair and distributed layout can help overcome some of the constraints imposed by nanometer CMOS process for high performance analog circuits in weak inversion region.
147 citations
TL;DR: A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented, which has a normal Miller capacitor still needed to provide an internal negative feedback loop and a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation.
Abstract: A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented in this paper. This IAC topology has, on one hand, a normal Miller capacitor, which is still needed to provide an internal negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation. A three-stage IAC amplifier was implemented and fabricated in a 0.35 μm CMOS technology. Experiment results show that the implemented IAC amplifier, driving a 150 pF load capacitance, achieved a gain-bandwidth product (GBW) of 4.4 MHz while dissipating only 30 μW power with a 1.5 V supply.
113 citations
"An ultra-low-voltage OTA in 28 nm U..." refers methods in this paper
...Table II employs the widely used figures of merit (FoM) for OTAs [8] to compare this work with other ultra-low-voltage OTAs....
[...]
...Section II reviews the design considerations for ultra-low-voltage OTAs....
[...]
...In order to support low supply voltages, pseudo-differential (PD) OTAs [3] and inverter-based subthreshold OTAs [4] have been proposed....
[...]