An Unconstrained Topological Via Minimization Problem for Two-Layer Routing
01 Jul 1984-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE)-Vol. 3, Iss: 3, pp 184-190
TL;DR: It is shown that the simplest problem of this type is NP-complete and a heuristic algorithm for topological via minimization is proposed and proposed.
Abstract: Based on graph theory, a study of via minimization problem is presented. We show that the simplest problem of this type is NP-complete and propose a heuristic algorithm for topological via minimization.
Citations
More filters
Book•
31 Jan 1993
TL;DR: This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.
Abstract: From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.
927 citations
01 Feb 1990
TL;DR: The current status of VLSI layout and directions for future research are addressed, and the field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered.
Abstract: The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided Placement and floorplanning for both the sea-of-gates and building-block designs are examined The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size Global routing based on a method of successive cuts on a chip is discussed This is a hierarchical top-down approach that is useful for both of the above designs A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered >
225 citations
TL;DR: The layer assignment problem for interconnect is the problem of determining which layers should be used for wiring the signal nets and an efficient algorithm for identifying essential vias is presented and discussed in this paper.
Abstract: The layer assignment problem for interconnect is the problem of determining which layers should be used for wiring the signal nets. The objective of the layer assignment problem in general is to minimize the number of vias required. Thus, it is also referred to as the via minimization problem. In a via minimization problem, if the topology of the given layout is fixed, the problem is referred to as a constrained via minimization (CVM) problem. On the other hand, if both the topology of the layout and the layer assignment are to be decided, it is referred to as an unconstrained via minimization (UVM) problem. In this paper, both the CVM and UVM problems are studied. For the CVM problems, efficient algorithms which can be easily modified to take extra constraints into consideration are proposed. Experimental results show that the proposed algorithms for the CVM problem are time efficient compared with existing algorithms and generate better (near-optimal) results. For the UVM problems, a new heuristic approach is presented which generates better results but takes longer computing time. In the CVM problem, some vias are "essential" to the given layout. That is, they have to be selected and cannot be replaced by other possible vias. An efficient algorithm for identifying essential vias is also presented and discussed in this paper.
115 citations
TL;DR: In this paper, the problem of wiring an arbitrary knock-knee layout (in a square grid with an arbitrary number of modules) in three and two layers using a small number of vias is investigated.
Abstract: The problem of wiring an arbitrary knock-knee layout (in a square grid with an arbitrary number of modules) in three and two layers using a small number of vias is investigated. A technique is proposed for transforming a knock-knee layout into a three-layer wirable layout by replacing knock-knees with 45 degrees wires. A 45 degrees replacing algorithm to achieve three-layer wirability is introduced. An efficient stretching technique to ensure two-layer wirability using 45 degrees wires is described. Conversion of an abstract layout into a corresponding physical layout is discussed. Experimental results are presented. >
106 citations
01 Oct 1987
TL;DR: This paper describes a graph theoretic algorithm which, given a particular layout, finds a layer assignment that requires the minimum number of vias and yields globally optimum results when the maximum junction degree is limited to three and has been fully implemented.
Abstract: This paper describes a graph theoretic algorithm which, given a particular layout, finds a layer assignment that requires the minimum number of vias. The time complexity of the algorithm is O(n /sup 3/) where n is the number of routing segments in the given layout. Unlike previous algorithms, this algorithm does not require the layout to be grid based and places no constraints on the location of vias or the number of wires that may be joined at a single junction. The algorithm yields globally optimum results when the maximum junction degree is limited to three and has been fully implemented.
84 citations
References
More filters
28 Jun 1971
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Abstract: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.
655 citations
TL;DR: In this paper, an efficient via minimization algorithm for certain types of two-layer printed circuit boards is developed which can be executed in polynomial time and yields solutions for routings with junctions of degrees varying from 2 to 8 and guarantees the minimum number of vias for routing with three or fewer line segments connected to each junction.
Abstract: Based on graph theory, an efficient via minimization algorithm for certain types of two-layer printed circuit boards is developed which can be executed in polynomial time. The algorithm yields solutions for routings with junctions of degrees varying from 2 to 8 and guarantees the minimum number of vias for routings with three or fewer line segments connected to each junction. Examples are given to illustrate various aspects of the algorithm. In addition, preassignment of line segments on a particular layer of the board due to certain prescribed board (or component) constraints is discussed.
106 citations
TL;DR: This paper describes the topological routing algorithm in detail, based on a circle graph representation of the net intersection information of the routing problem, which selects a maximal set of nets that can be routed without vias.
Abstract: A new approach to the two-dimensional routing utilizing two layers is proposed. It consists of two major steps, topological routing and geometrical mapping. This paper describes the topological routing algorithm in detail. Based on a circle graph representation of the net intersection information of the routing problem, a maximal set of nets that can be routed without vias are selected. The layer assignments for the selected nets are determined by a global analysis so that the total number of vias needed is minimum. The layer assignment problem turns out to be a maximum-cut problem on an edge-weighted graph and we developed a greedy algorithm for it. According to the layer assignments, the detailed topological routes are then generated.
102 citations
29 Jun 1981
TL;DR: An optimum layer assignment of interconnections in IC and two-layer PCB is derived through a global minimization of contacts or vias using a branch and bound technique.
Abstract: An optimum layer assignment of interconnections in IC and two-layer PCB is derived. The assignment is optimal in the sense that it is achieved through a global minimization of contacts or vias. The problem is formulated as a 0,1 integer program and solved using a branch and bound technique. There are no constraints on contact location or on the number of wires that can be connected at each contact. Applications of this procedure to VLSI circuits are discussed.
47 citations