Analog Circuit Design Using Tunnel-FETs

doi:10.1109/TCSI.2014.2342371

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Analog Circuit Design Using Tunnel-FETs

Journal Article•DOI•

Analog Circuit Design Using Tunnel-FETs

Behnam Sedighi¹, Xiaobo Sharon Hu¹, Huichu Liu², Joseph J. Nahas¹, Michael Niemier¹ - Show less +1 more•Institutions (2)

University of Notre Dame¹, Pennsylvania State University²

01 Jan 2015-IEEE Transactions on Circuits and Systems (IEEE)-Vol. 62, Iss: 1, pp 39-48

TL;DR: It is shown that TFETs are promising for low-power and low-voltage designs, wherein transistors are biased at low-to-moderate current densities and more than an order of magnitude increase in their DC voltage gain.

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Abstract: Tunnel-FET (TFET) is a major candidate for beyond-CMOS technologies. In this paper, the properties of the TFETs that affect analog circuit design are studied. To demonstrate how TFETs can enhance the performance or change the topology of the analog circuits, several building blocks such as operational transconductance amplifiers (OTAs), current mirrors, and track-and-hold circuits are examined. It is shown that TFETs are promising for low-power and low-voltage designs, wherein transistors are biased at low-to-moderate current densities. Comparing 14-nm III–V TFET-based OTAs with Si-MOSFET-based designs demonstrates up to 5 times reduction in the power dissipation of the amplifiers and more than an order of magnitude increase in their DC voltage gain. The challenges and opportunities that come with the special characteristics of TFETs, namely asymmetry, ambipolar behavior, negative differential resistance, and superlinear operation are discussed in detail.

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Design Of Analog Cmos Integrated Circuits

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Franziska Hoffmann

01 Jan 2016

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1,038 citations

Journal Article•DOI•

TFET-Based Circuit Design Using the Transconductance Generation Efficiency $ {g}_{m}/ {I}_{d}$ Method

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Leonardo Barboni¹, Mariana Siniscalchi¹, Berardi Sensale-Rodriguez²•Institutions (2)

University of the Republic¹, University of Utah²

11 Mar 2015-IEEE Journal of the Electron Devices Society

TL;DR: In this paper, the GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed to date for ultra-low power analog applications, which can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs.

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Abstract: Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this paper, we: 1) review the perspectives of such devices for low-power high-frequency analog integrated circuit applications (e.g., GHz operation with sub-0.1 mW power consumption); 2) discuss and employ a compact TFET device model in the context of the $g_{m}/I_{d}$ integrated analog circuit design methodology; and 3) compare several proposed TFET technologies for such applications. The advantages of TFETs arise since these devices can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs, which is due to the current turn-on mechanism being interband tunneling rather than thermionic emission. Starting from technology computer-aided design and/or analytical models for Si-FinFETs, graphene nano-ribbon (GNR) TFETs and InAs/GaSb TFETs at the 15-nm gate-length node, as well as InAs double-gate TFETs at the 20-nm gate-length node, we conclude that GNR TFETs might promise larger bandwidths at low-voltage drives due to their high current densities in the sub-threshold region. Based on this analysis and on theoretically predicted properties, GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed-to-date for ultra-low power analog applications.

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73 citations

Cites background from "Analog Circuit Design Using Tunnel-..."

...In terms of more complex circuits, a TFET differential folded cascode OTA is presented in [14] to show the benefits of TFETs having a higher gm/Id than traditional FETs....
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Journal Article•DOI•

Digital and analog TFET circuits: Design and benchmark

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Sebastiano Strangio¹, Sebastiano Strangio², Francesco Settino², Francesco Settino¹, Pierpaolo Palestri², Marco Lanuzza¹, Felice Crupi¹, David Esseni², Luca Selmi³, Luca Selmi² - Show less +6 more•Institutions (3)

University of Calabria¹, University of Udine², University of Modena and Reggio Emilia³

01 Aug 2018-Solid-state Electronics

TL;DR: This work investigates by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs) and highlights how differences in the I-V characteristics of FinFets and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

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Abstract: In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

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57 citations

Cites background or methods from "Analog Circuit Design Using Tunnel-..."

...In this respect, circuit simulations have attributed to TFETs the potential to outperform conventional MOSFETs in the ultralow voltage domain (VDD 0.4 V) in both analog [8–10] and digital [11–17] applications....
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...Another intrinsic advantage of TFETs over conventional MOSFETs stems from the lower temperature dependence of BtBT compared to thermionic emission [56], which may directly translate in less temperature sensitivity of TFET circuits....
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...On the other hand, the output conductance is lower due to the different electrostatics compared to MOSFETs [8]....
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...From a general perspective, the key messages of this study are: • the pros (i.e. low subthreshold swing and high output resistance) and cons (i.e. ambipolarity, unidirectionality, p- versus n-type asymmetry, large gate-to-drain intrinsic capacitance, higher sensitivity to variability sources) of TFETs with respect to MOSFETs can be balanced at best by adopting new circuit topologies with respect to standard CMOS solutions; • while research on TFETs focuses mostly on switches for digital circuits, TFETs exhibit potential interesting advantages also for analog and mixed-signal applications; these advantages might be emphasized in niche applications, by exploiting the low-temperature dependence of TFET operation; • the introduction of TFET in mainstream CMOS technologies will likely be limited to electronic systems operating at extremely reduced voltage (lower than 400mV) and by preferentially adopting an hybrid TFET/MOSFET implementation, which takes advantage of both transistor options....
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...After the initial report in [1], complementary-metal-oxide-semiconductor (CMOS) transistors based on band-to-band-tunneling (BtBT), usually referred to as Tunnel-FETs (TFETs), have been extensively explored as possible replacements of, or complements to, conventional MOSFETs for low-power/low-energy electronic circuits targeting a supply voltage VDD below 0.5 V [2–5]....
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Journal Article•DOI•

Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits

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Francesco Settino¹, Marco Lanuzza², Sebastiano Strangio¹, Felice Crupi², Pierpaolo Palestri¹, David Esseni¹, Luca Selmi¹ - Show less +3 more•Institutions (2)

University of Udine¹, University of Calabria²

12 Apr 2017-IEEE Transactions on Electron Devices

TL;DR: In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node.

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Abstract: In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage.

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54 citations

Cites background or methods from "Analog Circuit Design Using Tunnel-..."

...have used mixed-mode device-circuit simulations as available in TCAD tools and/or lookup table (LUT)-based simulations in the Verilog-A environment [10]–[14]....
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...The results of [10] highlighted that several analog circuit topologies have to be revised for a TFET implementation, due to the peculiar characteristics of the devices, such as the unidirectional conduction, the ambipolar leakage, the large output resistance, the large gate-to-drain capacitance, and the negative differential resistance (NDR)....
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...[10], however, embraced the optimistic assumption of a perfect symmetry between p- and n-type TFETs: in fact, p-TFET electrical characteristics were obtained by mirroring the n-TFET curves....
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...[10] reported an extensive analysis of TFET-based analog circuits and a systematic comparison with their MOSFET counterparts....
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Journal Article•DOI•

Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire Tunnel FET

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Sudhansu Mohan Biswal¹, Biswajit Baral¹, Debashis De², Angsuman Sarkar³•Institutions (3)

Silicon Institute of Technology¹, West Bengal University of Technology², Kalyani Government Engineering College³

01 Mar 2016-Superlattices and Microstructures

TL;DR: In this article, the effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire (NW) Tunnel FET (TFET) was analyzed.

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38 citations

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References

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Open Access

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Book•

Analysis and Design of Analog Integrated Circuits

[...]

Paul R. Gray, Robert G. Meyer

01 Jan 1977

TL;DR: In this article, the authors combine bipolar, CMOS and BiCMOS analog integrated circuits into a unified treatment that stresses their commonalities and highlights their differences, and provide valuable insights into the relative strengths and weaknesses of these important technologies.

...read moreread less

Abstract: The Fifth Edition of this academically rigorous text provides a comprehensive treatment of analog integrated circuit analysis and design starting from the basics and through current industrial practices. The authors combine bipolar, CMOS and BiCMOS analog integrated-circuit design into a unified treatment that stresses their commonalities and highlights their differences. The comprehensive coverage of the material will provide the student with valuable insights into the relative strengths and weaknesses of these important technologies.

...read moreread less

4,717 citations

Journal Article•DOI•

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

[...]

Alan Seabaugh¹, Qin Zhang¹•Institutions (1)

University of Notre Dame¹

25 Oct 2010

TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.

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Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

...read moreread less

1,389 citations

"Analog Circuit Design Using Tunnel-..." refers background in this paper

...This is often coined as ambipolar behavior and is caused by minority carrier tunneling [2]....
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...Amongst many proposals, TunnelFETs (TFETs) have shown to be a promising choice for digital circuits [1]; TFETs can have a subthreshold swing below 60 mV/dec, enabling a high on-current to off-current ratio [2], [3]....
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Journal Article•DOI•

New Phenomenon in Narrow Germanium p − n Junctions

[...]

Leo Esaki

15 Jan 1958-Physical Review

1,318 citations

"Analog Circuit Design Using Tunnel-..." refers background in this paper

...The phenomenon causing NDR is the same as that of a tunneling (Esaki) diode [21]....
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Design Of Analog Cmos Integrated Circuits

[...]

Franziska Hoffmann

01 Jan 2016

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1,038 citations

"Analog Circuit Design Using Tunnel-..." refers background or methods in this paper

...The unity-gain frequency is given by [18]...
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...It is instructive to compare the parameters of the level-1 SPICE MOS model that estimates the drain current as [18]...
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...Achieving a large DC gain in the CMOS OTA is possible by increasing the length of transistors or by gain-boosting [18], but this further increases the chip area and power dissipation....
[...]
...By increasing of the input transistors all the aforementioned specifications of an opamp (or OTA) will improve [18], [27]....
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Journal Article•DOI•

A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

[...]

Fernando Silveira, Denis Flandre¹, Paul Jespers¹•Institutions (1)

Université catholique de Louvain¹

01 Sep 1996-IEEE Journal of Solid-state Circuits

TL;DR: In this paper, a new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used.

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Abstract: A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over DC drain current g/sub m//I/sub D/ and the normalized current I/sub D//(W/L). The g/sub m//I/sub D/ indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA).

...read moreread less

604 citations