Analysing the Impact of Various Deterministic Noise Sources on Jitter in a CMOS Inverter
07 Mar 2019-pp 208-211
TL;DR: The results obtained from the semi-analytical jitter estimation approach presented in the paper are compared with the results obtained with full SPICE based simulations.
Abstract: This paper presents an analysis of jitter due to various deterministic noise sources in a CMOS inverter. The results obtained from the semi-analytical jitter estimation approach presented in the paper are compared with the results obtained from full SPICE based simulations. For the estimation of jitter, EMPSIJ method [1] is used in the paper. The paper also discusses the sensitivity of various noise paths on jitter.
Citations
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TL;DR: Noise impact is the most sounds are subjective evaluation, hearing, and can significantly affect human health and wellbeing and the effect of limited accuracy means that the quantitative effect is inherent in the implementation of any digital system.
8 citations
TL;DR: An efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources is presented.
Abstract: This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc.
6 citations
Cites background from "Analysing the Impact of Various Det..."
...PROBLEM FORMULATION In CMOS inverters, noise at the output causes the deviation of signal transition edge (rising/falling) from the nominal position and leads to time interval error (TIE) [23]....
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...Next, using the analytically computed v̂rn (t) and using the EMPSIJ method [26], TIE and PSIJ are evaluated....
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...Next, TIE can be estimated based on the slope of the rising/falling edge of the output signal [26]....
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...In this paper, a simplified semi-analytical approach is developed for the analysis of TIE (as well as the jitter) at the output of a delayline or tapered buffer that are designed using CMOS inverters....
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...In this method, TIE at the rising/falling edge of a bit is estimated from the noise voltage at the output v̂rn (tm) by dividing it with the slope (αtm ) of the output response at the mid-point (tm)....
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DOI•
TL;DR: In this paper , a self-calibrated low-dropout regulator (LDO) was proposed to eliminate the use of a bandgap reference circuit and its large flicker noise contribution in traditional power regulators to achieve ultralow noise performance.
Abstract: This article proposes a Ka-band transceiver with an integrated local oscillator (LO) generator and multiple low dropout regulators (LDOs) to eliminate the strict requirements to the external power supply network. The proposed self-calibrated LDO eliminates the use of a bandgap reference circuit and its large flicker noise contribution in traditional power regulators to achieve ultralow-noise performance. The output of the proposed LDO is self-calibrated with temperature and process variations by autoconfiguring the feedback coefficient through a digital loop to guarantee the stable performance of its loaded high-speed circuits. The stable gain and output power of the transceiver with temperature variation are achieved by on-chip multiple self-compensation schemes, which include a self-sensing LDO for the power amplifier, a constant- $G_{\!m}$ bias circuit for the amplification stages, and the temperature-compensated intermediate-frequency amplifiers (TC IFAs) with proportional-to-absolute-temperature (PTAT) gain to further compensate for the gain deviation caused by the second-order effect and large-signal performance difference. Implemented in 65-nm CMOS technology, measurements indicate that the output noise of the proposed LDO is as low as 15 nV/sqrt (Hz) at 10-kHz offset and the integrated power network greatly reduces the noise influence on the LO signal compared with the traditional bandgap-referenced LDO. Furthermore, due to the adoption of the proposed temperature compensation scheme, the small-signal gains of the receiver and transmitter only fluctuate by 1.1 and 1.3 dB from $- 40\,\,^{\circ }\text{C}$ to $85~^{\circ }\text{C}$ , respectively, and the output saturated power of the transmitter varies by 0.7 dBm over the entire temperature range.
19 Sep 2022
TL;DR: In this paper , the authors demonstrate that using sub-sampling mixer topology can be the right choice to implement a millimeter-wave (mmW) receiver, which allows to reduce the burden of a 77 GHz LO distribution chain, in terms of area and consumption, while preserving RF performances.
Abstract: This paper demonstrates that using sub-sampling mixer topology can be the right choice to implement a millimeter-wave (mmW) receiver. In a 77 GHz radar receiver, it allows to reduce the burden of a 77 GHz LO distribution chain, in term of area and consumption, while preserving RF performances. Demonstration is done from two topologies of x3 sub-sampling mixers implemented in 28-nm FD-SOI CMOS technology. The best proposed passive mixer exhibits a -2.1 dB conversion gain ( $G$ cv ), a IdB input-referred compression power (ICPldB) of +3.5 dBm, and a 16.8 dB Single Side Band Noise Figure (NF SSB ). The mixer LO signal shaping consumption is 32 mW on a 1.2 V supply while the passive mixer core does not require any DC power.
TL;DR: In this article , it is demonstrated that at the final output of the inverter chain, power supply induced jitter does not necessarily increase with the number of inverter stages, and the presented investigation is validated by comparing the results using a semianalytical method with SPICE based simulations.
Abstract: This paper presents novel observations and physical insights on jitter in a chain of CMOS inverters. It is demonstrated that at the final output of the inverter chain, power supply induced jitter does not necessarily increase with the number of inverter stages. The presented investigation is validated by comparing the results using a semianalytical method with SPICE based simulations. The proposed observations are also validated using measurement results obtained by two measurement setups.
References
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30 May 1994
TL;DR: The effects of thermal noise in transistors on timing jitter in CMOS ring-oscillators composed of source-coupled differential resistively-loaded delay cells is investigated and the relationship between delay element design parameters and the inherent thermal noise-induced jitter of the generated waveform are analyzed.
Abstract: in this paper the effects of thermal noise in transistors on timing jitter in CMOS ring-oscillators composed of source-coupled differential resistively-loaded delay cells is investigated. The relationship between delay element design parameters and the inherent thermal noise-induced jitter of the generated waveform are analyzed. These results are compared with simulated results from a Monte-Carlo analysis with good agreement. The analysis shows that timing jitter is inversely proportional to the square root of the total capacitance at the output of each inverter, and inversely proportional to the gate-source bias voltage above threshold of the source-coupled devices in the balanced state. Furthermore, these dependencies imply an inverse relationship between jitter and power consumption for an oscillator with fixed output period. Phase noise and timing jitter performance are predicted to improve at a rate of 10 dB per decade increase in power consumption. >
294 citations
Book•
19 Nov 2007
TL;DR: The fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes are introduced, and Dr. Li provides powerful new tools for solving these problems quickly, efficiently, and reliably.
Abstract: State-of-the-art JNB and SI Problem-Solving: Theory, Analysis, Methods, and ApplicationsJitter, noise, and bit error (JNB) and signal integrity (SI) have become today's greatest challenges in high-speed digital design. Now, there's a comprehensive and up-to-date guide to overcoming these challenges, direct from Dr. Mike Peng Li, cochair of the PCI Express jitter standard committee.One of the field's most respected experts, Li has brought together the latest theory, analysis, methods, and practical applications, demonstrating how to solve difficult JNB and SI problems in both link components and complete systems. Li introduces the fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes. He guides readers from basic math, statistics, circuit and system models all the way through final applications. Emphasizing clock and serial data communications applications, he covers JNB and SI simulation, modeling, diagnostics, debugging, compliance testing, and much more.Coverage includes? JNB component classification, interrelationships, measurement references, and transfer functions Statistical techniques and signal processing theory for quantitatively understanding and modeling JNB and related components Jitter, noise, and BER: physical/mathematical foundations and statistical signal processing views Jitter separation methods in statistical distribution, time, and frequency domains Clock jitter in detail: phase, period, and cycle-to-cycle jitter, and key interrelationships among them PLL jitter in clock generation and clock recovery Jitter, noise, and SI mechanisms in high-speed link systems Quantitative modeling and analysis for jitter, noise, and SI Testing requirements and methods for links and systems Emerging trends in high-speed JNB and SI As data rates continue to accelerate, engineers encounter increasingly complex JNB and SI problems. In Jitter, Noise, and Signal Integrity at High-Speed, Dr. Li provides powerful new tools for solving these problemsi??quickly, efficiently, and reliably.Preface xvAcknowledgements xxiAbout the Author xxiiiChapter 1: Introduction 1Chapter 2: Statistical Signal and Linear Theory for Jitter, Noise, and Signal Integrity 27Chapter 3: Source, Mechanism, and Math Model for Jitter and Noise 75Chapter 4: Jitter, Noise, BER (JNB), and Interrelationships 109Chapter 5: Jitter and Noise Separation and Analysis in Statistical Domain 131Chapter 6: Jitter and Noise Separation and Analysis in the Time and Frequency Domains 163Chapter 7: Clock Jitter 185Chapter 8: PLL Jitter and Transfer Function Analysis 209Chapter 9: Jitter and Signal Integrity Mechanisms for High-Speed Links 253Chapter 10: Modeling and Analysis for Jitter and Signaling Integrity for High-Speed Links 281Chapter 11: Testing and Analysis for Jitter and Signaling Integrity for High-Speed Links 309Chapter 12: Book Summary and Future Challenges 345Index 353
178 citations
TL;DR: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ).
Abstract: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.
45 citations
"Analysing the Impact of Various Det..." refers methods in this paper
...EMPSIJ Method As discussed earlier, there are several methods available in the literature [11] for the estimation of jitter....
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10 Oct 2011
TL;DR: The transfer function of a supply voltage fluctuation to jitter is analytically solved for a single ended buffer in closed-form expressions and validated by comparison with HSPICE simulation.
Abstract: In this paper, the transfer function of a supply voltage fluctuation to jitter is analytically solved for a single ended buffer in closed-form expressions. The expressions for the jitter transfer function is validated by comparison with HSPICE simulation, and applied to an example for statistical jitter estimation.
31 citations
TL;DR: An efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise is presented.
Abstract: This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.
30 citations
Additional excerpts
...sources in an inverter is presented in [10], where the analysis is done by considering three noise sources from the supply, the data input and the ground....
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