Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback
01 Mar 2021-IEEE Journal of Solid-state Circuits (Institute of Electrical and Electronics Engineers (IEEE))-Vol. 56, Iss: 3, pp 729-738
TL;DR: The design principles and circuit details of a single-bit continuous-time delta-sigma ADC that achieves 13.3-bit resolution over a 20-MHz signal bandwidth are presented and mixed-signal calibration is enabled by the DAC architecture.
Abstract: We present the design principles and circuit details of a single-bit continuous-time delta-sigma ADC that achieves 13.3-bit resolution over a 20-MHz signal bandwidth. The modulator, which operates at a sampling rate of 2.56 GHz in a 65-nm CMOS process, uses a 2 $\times $ time-interleaved ADC to address the problem of comparator metastability. A 4 $\times $ time-interleaved virtual-ground-switched resistive FIR feedback DAC is used for low distortion and power-efficient operation. Interleaving artifacts caused by DAC-element mismatch are addressed by mixed-signal calibration, which is enabled by the DAC architecture. The decimator is implemented using poly-phase techniques. A prototype modulator, which operates with a 1.1-V supply, achieves 82.1-dB peak SNDR and THD of 98.6 dBc while consuming 11.3 mW. The resulting Schreier FoM is 174.1 dB. The decimator dissipates 13.5 mW.
Citations
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TL;DR: In this article , a 3-0 sturdy-multi-stage noise-shaping (SMASH) continuous-time (CT) incremental delta-sigma analog-to-digital converter (ADC) is presented.
Abstract: This article shows the design of a wideband 3-0 sturdy-multi-stage noise-shaping (SMASH) continuous-time (CT) incremental delta–sigma (I- $\boldsymbol {\Delta \Sigma }$ ) analog-to-digital converter (ADC). The two stages’ quantizers (QTZs) are implemented by a single re-configurable multibit (MB) asynchronous (A)SAR ADC. The digital-to-analog converter (DAC) nonlinearities are suppressed by reconfiguring the asynchronous successive-approximation register (ASAR) ADC from 2 to 5 b, and correspondingly, the DACs dynamically switch from 1.5- to 4-b tri-level outputs within each Nyquist conversion cycle. This results in a DAC-calibration-free MB operation. A two-tap FIR filter is implemented in the feedback DACs to reduce jitter requirements in the initial 1.5-b cycles. Through the design representation, a detailed fundamental comparison between an X-0 SMASH architecture and an X-order single-loop modulator is discussed. This discussion highlights the introduction of an efficient tri-level combination between the MSB and the LSBs of the ASAR QTZ. The resulting SMASH CT I- $\boldsymbol {\Delta \Sigma }$ modulator was fabricated in 28-nm CMOS technology with an active area of 0.125 mm2. It achieves 97-dB spurious-free dynamic range (SFDR) without calibration, 89-dB dynamic range (DR), and 81.2-dB SNDR in a 1-MHz bandwidth (BW). It consumes 3.6 mW from a single 0.9-V supply. The design shows very good robustness across different tested samples, supply variations, and across temperatures from −20 °C to 80 °C.
4 citations
TL;DR: In this paper , a hybrid 4th-order delta-sigma modulator (DSM) was proposed, which combines a continuous-time (CT) loop filter and a DT passive 2nd-order noise-shaping SAR (NSSAR).
Abstract: This paper presents a hybrid 4th-order delta-sigma modulator (DSM). It combines a continuous-time (CT) loop filter and a discrete-time (DT) passive 2nd-order noise-shaping SAR (NSSAR). Since the 2nd-order NS-SAR is robust against PVT variation, the stability of this 4th-order DSM is similar to that of a 2nd-order CT-DSM. The CT loop filter is based on single-amplifier bi-quad (SAB) structure. As a result, only one OTA is used to achieve 4th-order noise shaping, leading to a high power efficiency. Moreover, this work implements both excess loop delay (ELD) compensation and an input feedforward path inside the NS-SAR in the charge domain, further reducing the circuit complexity and the OTA power. Overall, this work achieves 81 dB SNDR over 12.5 MHz with 3.7 mW power, leading to a Schreier FoM of 176 dB.
2 citations
TL;DR: The zapped, virtual-ground-switched dual return-to-open DAC which is immune to ISI and other transition-dependent errors is introduced and FIR feedback facilitates chopping, improves clock-jitter sensitivity and the loop filter’s linearity.
Abstract: We present design techniques for single-bit continuous-time delta–sigma modulators that attain high resolution (>16 bits) over a bandwidth (BW) that is more than ten times the audio range. We introduce the zapped, virtual-ground-switched dual return-to-open DAC which is immune to ISI and other transition-dependent errors. FIR feedback facilitates chopping, improves clock-jitter sensitivity and the loop filter’s linearity. We show that the compensation FIR DAC, which is typically bulky, can be implemented in an extremely power- and area-efficient manner in a single-bit modulator using a capacitive DAC and passive summation. Thanks to these techniques, the fabricated prototype achieves 103.2-/104.3-dB signal to noise and distortion ratio (SNDR)/signal to noise ratio (SNR) in a 250-kHz bandwidth while operating at 48 MS/s. Consuming 17.7 mW from a 1.8-V supply, the modulator occupies 1.1 mm 2 in a 180-nm CMOS process. The Schreier (SNDR) figure of merit (FoM) is 174.7 dB.
2 citations
28 May 2022
TL;DR: In this article , a modified Look-Up-Table (LUT) based DAC foreground calibration for multi-bit continuous-time Delta-Sigma modulators is presented, which reduces the correction complexity while maintaining the same performance as current state-of-the-art solutions towards static and dynamic errors.
Abstract: This paper presents a modified Look-Up-Table (LUT) based DAC foreground calibration for multi-bit continuous-time Delta-Sigma Modulators. The feedback DAC in DSMs is usually a performance bottleneck, as all of its errors directly add at the input node. Fore - or background error correction based on LUT can efficiently eliminate the DAC errors, but can also impose significant circuit overhead in the digital and analog domain. The presented method reduces the correction complexity while maintaining the same performance as current state-of-the-art solutions towards static and dynamic errors.
1 citations
TL;DR: In this paper , the authors demonstrate the circuit technique of a highly power-efficient continuous-time (CT) Delta-sigma modulator (DSM) based on a switched-capacitor (SC) feedback digital-to-analog converter (DAC) and a passive front-end low-pass filter (LPF).
1 citations
References
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Book•
08 Nov 2004
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
2,200 citations
"Analysis and Design of a 20-MHz Ban..." refers background or methods in this paper
...Our design uses FIR feedback to further reduce clock jitter sensitivity and improve linearity [8]....
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...It is well known that the error due to ISI is proportional to the DAC’s “transition” sequence—namely, one that is formed by the absolute value of the height of the transition in the DAC waveform at the preceding clock edge [8]....
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...noisy and complex and have many more distortion-introducing mechanisms when compared to their resistive counterparts [8]....
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...based on the analysis in [8] show that this will limit the harmonic distortion of the CT M to about 65 dB....
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28 Mar 2013
TL;DR: This paper presents a low-power solution based on a highly digital multibit quantizer with embedded feedback to compensate for finite opamp bandwidth along with ELD.
Abstract: Recently reported continuous-time (CT) ΔΣ modulators with opamp bandwidth compensation and high-order single-opamp integrators have achieved FoM values well below 100fJ/conv-step [1-3]. With loop-filter power greatly reduced, power dissipation in multibit quantizers becomes especially significant. For example, the quantizer in [2] accounts for 2.8mW of 8.5mW total power dissipation. Also, the input capacitance of multibit quantizers and the output parasitics of excess loop delay (ELD) compensation DACs result in increased power demand for summing circuits. To minimize power dissipation, two recent works use 1b quantizers with FIR DACs and replace ELD compensation DACs with a DAC followed by analog filter [3] or with feedback to the pre-amplifier [4]. ELD compensation may also be realized using digital logic following the quantizer [5]. This paper presents a low-power solution based on a highly digital multibit quantizer with embedded feedback to compensate for finite opamp bandwidth along with ELD. The quantizer consumes less than 10% of the total power and simplifies the analog circuits into a single DAC plus a feedforward loop filter with relaxed opamp requirements. Digital correction at the modulator output suggested by early work [6] is employed to shape DAC mismatch with the inherent noise transfer function (NTF) and to further relax circuit constraints. These digitally assisted techniques enable a CT ΔΣ modulator to achieve an FoM below 28fJ/conv-step.
90 citations
"Analysis and Design of a 20-MHz Ban..." refers methods in this paper
...Prior-art CT Ms [1]–[6] have used multibit quantizers and a low oversampling ratio (OSR) to achieve such a combination of resolution and bandwidth....
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TL;DR: The new ISI-shaping algorithm results in significant improvement over previous schemes including the modified Mismatch Shaper (MMS) which also addresses ISI error and practically eliminates the need for conventional ISI mitigation techniques.
Abstract: A new digital signal processing approach to shaping intersymbol interference (ISI) and static mismatch errors simultaneously in oversampled multi-level digital to analog converters (DAC) has recently been proposed. In this paper, a mathematical framework is established for analyzing ISI errors as well as comparing the ISI sensitivities of different mismatch shaping algorithms. The framework is used to analyze the fundamental problems of popularly used algorithms such as data-weighted-averaging (DWA) in the presence of nonlinear ISI: Large-signal even-order distortion and frequency modulated harmonics at low signal levels. The new ISI-shaping algorithm results in significant improvement over previous schemes including the modified Mismatch Shaper (MMS) which also addresses ISI error. The new ISI shaper, while increasing the digital complexity, practically eliminates the need for conventional ISI mitigation techniques such as time consuming, layout-critical, non-automated and process specific analog design methods. The advantages of ISI shaping is further verified on an experimental audio DAC with simple non-return-to-zero (NRZ) current steering segments implemented in a 45 nm CMOS process and running off a single-phase clock of only 3.072 MHz.
58 citations
"Analysis and Design of a 20-MHz Ban..." refers background in this paper
...dynamic performance [7] (which is limited by inter-symbol...
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...The current is maximum when the analog input is small (where the CT M output sequence rapidly jumps between ±1 [7]) and reduces when the input becomes larger in magnitude (when the modulator output does not switch as rapidly)....
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TL;DR: This paper presents a compact and power efficient third-order continuous-time (CT) delta-sigma analog-to-digital converter (ADC) with a single operational transconductance amplifier (OTA).
Abstract: This paper presents a compact and power efficient third-order continuous-time (CT) delta-sigma ( $\Delta \Sigma $ ) analog-to-digital converter (ADC) with a single operational transconductance amplifier (OTA). A 4-bit second-order fully passive noise-shaping (NS) successive-approximation-register (SAR) ADC is employed as the quantizer while inherently provides two additional NS orders. Fabricated in 40-nm CMOS, the prototype occupies 0.029 mm2 of active area and consumes 1.16 mW of power when clocked at 500-MHz sampling frequency. The proposed CT $\Delta \Sigma $ ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.4 dB over 12.5-MHz bandwidth, yielding a Walden figure of merit (FoM) of 17 fJ/conversion-step.
43 citations
TL;DR: The method enables the determination of loop filter coefficients to an arbitrary DAC pulse shape without resorting to z-domain analysis, and helps derive topologies to compensate CTDSMs with FIR feedback DACs, as well as give closed form expressions for the coefficients of the compensated modulator.
Abstract: We present a technique for determining the coefficients of the loop filter in a continuous-time delta sigma modulator (CTDSM) from the corresponding discrete time prototype. The method, which is based on computing the moments of the feedback DAC pulse shape, enables the determination of loop filter coefficients to an arbitrary DAC pulse shape without resorting to z-domain analysis. This not only simplifies the algebra, but also gives new insights into modulator operation. The technique helps derive topologies to compensate CTDSMs with FIR feedback DACs, as well as give closed form expressions for the coefficients of the compensated modulator. Finally, we give simple formulae for coefficients to compensate for excess loop delay in CTDSMs with arbitrary DAC pulses.
35 citations
"Analysis and Design of a 20-MHz Ban..." refers background in this paper
...eight-tap FIR-DAC (DAC22-C(z)) stabilize the loop for the delay introduced by F(z) [15]....
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