Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
01 Feb 2014-IEEE Transactions on Very Large Scale Integration Systems (IEEE)-Vol. 22, Iss: 2, pp 343-352
TL;DR: An analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived so that designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design.
Abstract: The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply.
Citations
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TL;DR: A new low-offset low-power dynamic comparator for analog-to-digital converters is introduced that benefits from two stages and two operational phases to reduce the offset voltage caused by the mismatch effect inside the positive feedback circuit.
61 citations
TL;DR: A low-power comparator using pMOS transistors at the input of the preamplifier of the comparator as well as the latch stage that reduces the power consumption and provides 30% better comparison speed at the same offset and almost the same noise budgets.
Abstract: A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process–VDD–temperature corners, and Monte Carlo simulations along with silicon measurements in $0.18~\mu \text{m}$ . The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input $V_{\text {cm}}$ range in $f_{\text {clk}} = 500$ MHz.
57 citations
TL;DR: This work investigates by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs) and highlights how differences in the I-V characteristics of FinFets and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.
Abstract: In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.
57 citations
Cites background from "Analysis and Design of a Low-Voltag..."
...The conventional and double tail [84] architectures sketched in Fig....
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TL;DR: In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node.
Abstract: In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage.
54 citations
Cites background or methods from "Analysis and Design of a Low-Voltag..."
...11(a), and the double-tail structure proposed in [38] and here illustrated in Fig....
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...In the double-tail topology Itail1 > Itail2 is maintained for proper design as indicated in [38]....
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...Architectures of the (a) conventional dynamic comparator and the (b) double-tail comparator [38] simulated in this paper....
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DOI•
24 Sep 2018TL;DR: Novel neuroinspired approaches are used to design a smart ADC that could be trained in real time for general purpose applications and break through conventional ADC limitations, and integrates emerging memristor technology with CMOS.
Abstract: The analog-to-digital converter (ADC) is a principal component in every data acquisition system. Unfortunately, modern ADCs tradeoff speed, power, and accuracy. In this paper, novel neuroinspired approaches are used to design a smart ADC that could be trained in real time for general purpose applications and break through conventional ADC limitations. Motivated by artificial intelligent learning algorithms and neural network architectures, the proposed ADC integrates emerging memristor technology with CMOS. We design a trainable four-bit ADC with a memristive neural network that implements the online gradient descent algorithm. This supervised machine learning algorithm fits multiple application specifications such as full-scale voltage ranges and sampling frequencies. Theoretical analysis, as well as simulation results, demonstrate highly powerful collective properties, including reconfiguration, mismatch self-calibration, adaptation to dynamic voltage and frequency scaling, noise tolerance, and power consumption optimization. The proposed ADC achieves 8.25 fJ/conv FOM, 3.7 ENOB, 0.4 LSB INL, and 0.5 LSB DNL. These promising properties make it a leading contender for general purpose and emerging data driven applications.
49 citations
Cites background from "Analysis and Design of a Low-Voltag..."
...Consequently, this will increase the area and power consumption substantially, as calculated in Table III based on [11][46][58][59]....
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References
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18 Jun 2007
TL;DR: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage, which enables fast operation over a wide common-mode and supply voltage range as discussed by the authors.
Abstract: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time
587 citations
TL;DR: In this paper, the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage was investigated for a latch-type voltage sense amplifier with a high-impedance differential input stage.
Abstract: A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 V/sub DD/ is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input DC voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.
450 citations
"Analysis and Design of a Low-Voltag..." refers background in this paper
...1 [1], [17]....
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...In [17], it has been shown that an input common-mode voltage of 70% of the supply voltage is optimal regarding speed and yield....
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...Half of the supply voltage is considered to be the threshold voltage of the comparator following inverter or SR latch [17]....
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TL;DR: This brief reviews existing solutions to minimize the kickback noise and proposes two new ones and HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.
Abstract: The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.
324 citations
"Analysis and Design of a Low-Voltag..." refers background in this paper
...” In [16], it has been shown that the fastest and most power efficient comparators generate more kickback noise....
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...Recently, many comprehensive analyses have been presented, which investigate the performance of these comparators from different aspects, such as noise [11], offset [12], [13], and [14], random decision errors [15], and kick-back noise [16]....
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...Besides, for some applications where kickback becomes important, it is possible to apply simple kickback reduction techniques, such as neutralization [16] to remarkably reduce the kickback noise (See Fig....
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TL;DR: A time-domain analysis is proposed that accounts for the time varying nature of the circuit exploiting some basic results from the solution of stochastic differential equations and the resulting symbolic expressions allow focusing designers' attention on the most influential noise contributors.
Abstract: The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compensated for by calibration, noise can irreparably hinder performance and is less straightforward to be accounted for at design time. This paper presents a method to estimate the input referred noise in fully dynamic regenerative comparators leveraging a reference architecture. A time-domain analysis is proposed that accounts for the time varying nature of the circuit exploiting some basic results from the solution of stochastic differential equations. The resulting symbolic expressions allow focusing designers' attention on the most influential noise contributors. Analysis results are validated by comparison with electrical simulations and measurement results from two ADC prototypes based on the reference comparator architecture, implemented in 0.18-mum and 90-nm CMOS technologies.
277 citations
"Analysis and Design of a Low-Voltag..." refers methods in this paper
...Since the comparator offset [11] can be reduced by using known techniques [3], the main focus of this paper is the comparator speed and power dissipation....
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