Analysis of a serial link for power supply induced jitter
Citations
45 citations
Additional excerpts
...The TIE can be analytically calculated by modeling the output response of the circuit [20], [21]....
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30 citations
Cites result from "Analysis of a serial link for power..."
...In [11] and [12], initial results of analysis of PSIJ based on separating the large signal response and small signal noise output were introduced....
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Cites methods from "Analysis of a serial link for power..."
...A delay-based technique for a chain of buffers, which also requires IFFT computation, can be found in [24] and via analytical techniques in [25] and [26]....
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...The method is generic in nature and the related discussions are presented in the context of currentmode (CM) driver circuits (which are commonly used in highspeed serial links, such as USB, MIPI, and so on [26]), with the following specific contributions....
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7 citations
Cites background from "Analysis of a serial link for power..."
...Various studies on the deterministic noise and PSIJ have been reported in literature [5]–[9]....
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References
178 citations
"Analysis of a serial link for power..." refers background in this paper
...Due to power supply fluctuations, a significant amount of jitter is introduced in the system which can be PJ and BUJ [5]....
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...DJ can further be classified as Periodic Jitter (PJ), Data Dependent Jitter (DDJ) and Bounded Uncorrelated Jitter (BUJ) [4]....
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31 citations
"Analysis of a serial link for power..." refers background in this paper
...Such analyses are addressed in earlier literature for single ended buffers [6][7]....
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17 citations
"Analysis of a serial link for power..." refers background in this paper
...The timing requirements are becoming the most stringent as the interconnect and packaging industry is not advancing as fast as device technology [2]....
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