Analysis of Secret Key Revealing Trojan Using Path Delay Analysis for Some Cryptocores
TL;DR: This work has been extended from the RTL design stage to the pre fabrication stage of ASIC platform where area and power analysis have been made to distinguish the affected core from a normal core in 180nm technology node.
Abstract: The design outsourcing of the IC supply chain across the globe has been witnessed as a major trend of the semiconductor design industry in the recent era. The increasing profit margin has been a major boost for this trend. However, the vulnerability of the introduction of malicious circuitry (Hardware Trojan Horses) in the untrusted phases of chip development has been a major deterrent in this cost effective design methodology. Analysis, detection and correction of such Trojan Horses have been the point of focus among researchers over the recent years. In this work, analysis of a secret key revealing Hardware Trojan Horse is performed. This Trojan Horse creates a conditional path delay to the resultant output of the cryptocore according to the stolen bit of secret key per iteration. The work has been extended from the RTL design stage to the pre fabrication stage of ASIC platform where area and power analysis have been made to distinguish the affected core from a normal core in 180nm technology node.
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26 Jun 2015
TL;DR: An intelligent architecture, Runtime Trust Neural Architecture (RTNA) based on Adaptive Resonance Theory (ART 1) neural network, which when incorporated with the SOC architecture can prevent it at runtime from being compromised confidentially.
Abstract: With the entry into the embedded domain, security of SOC architectures has become an arena of importance. However, complexity and cost factors have forced us to outsource the VLSI design phases across the globe. Such sites may not be trusted and threat lies in the introduction of malicious intrusions at any stage of the design flow. Such malicious intrusions, also known as Hardware Trojan Horses (HTH) remain dormant during the testing phase but get triggered at runtime and threaten the integrity and confidentiality of the chip. In this paper, we focus on threat to confidentiality. HTH threatens the confidentiality of such chips by leaking the secret information at runtime. We propose an intelligent architecture, Runtime Trust Neural Architecture (RTNA) based on Adaptive Resonance Theory (ART 1) neural network, which when incorporated with the SOC architecture can prevent it at runtime from being compromised confidentially. Low area and low power overhead of our proposed RTNA on practical crypto SOC architectures as obtained in the experimental results confirm its practical implementation. Hardware implementation of trust generation at runtime, use of unsupervised learning and use of an intelligent architecture are the novelties of this work.
13 citations
Cites background or methods from "Analysis of Secret Key Revealing Tr..."
...A similar scenario using the parameter of path delay has been demonstrated in [21]....
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...HTH implemented has the structure depicted in [5], [21]....
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...Introduction of HTH can make these security critical SOC architectures confidentially compromised [5], [21]....
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TL;DR: A new CAD model is proposed, which at first estimates a resistance distribution profile of the PDN based on geometric parameters of the chip and electrical parameter of the interconnects (sheet resistance), and then it is mapped with the circuit grid to perform the exact PDN analysis.
Abstract: Incorporation of power distribution network (PDN) in computer-aided design (CAD) of integrated circuits (ICs) is essential in the recent era. In order to reduce the overall power requirement, the common practice is to reduce the supply voltage. The lowering of supply voltage results in stiffening noise margin and hence increasing the effects of supply voltage fluctuation due to power supply noise. From recent research works, it is also evident that the fluctuation in supply voltage is increasing with scaling down of technology node. A proper estimation of overall power dissipation can only be performed through appropriate and exact parametric extraction of the circuit along with the PDN. Typically there exist many models of voltage fluctuation, which can be utilized to analyze the PDN. In this paper, we propose a new CAD model, which at first estimates a resistance distribution profile of the PDN based on geometric parameters of the chip and electrical parameter of the interconnects (sheet resistance), and then it is mapped with the circuit grid to perform the exact PDN analysis. To the best of our knowledge our proposed model is the first of its kind in regard to PDN analysis. We have chosen one ISCAS 85 benchmark circuit and cryptocores (DES, AES) as SOC applications for our analysis. We have used MATLAB and Mentor Graphics Pyxis tool for our simulation and analysis.
References
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TL;DR: A classification of hardware Trojans and a survey of published techniques for Trojan detection are presented.
Abstract: Editor's note:Today's integrated circuits are vulnerable to hardware Trojans, which are malicious alterations to the circuit, either during design or fabrication. This article presents a classification of hardware Trojans and a survey of published techniques for Trojan detection.
1,227 citations
"Analysis of Secret Key Revealing Tr..." refers background in this paper
...The authors in [1, 2] present a detailed study of classification of Hardware Trojans and a survey of published techniques of Trojan detection....
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...parts, microcontrollers, network processors, digital signal processors (DSP) or a modification in firmware like FPGA bitstreams [1]....
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...The effects of hardware Trojans can range from unsuccessful functional operation of IC to the detoriation of reliability and expected lifetime of ICs [1, 2]....
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...However, the IP blocks, models and standard cells used by the designer during the design process and by the foundry during the post design process are considered untrusted [1]....
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Book•
01 Jan 2015
TL;DR: This book includes the following chapters: Introduction to Modern Symmetric-Key Ciphers, Mathematics of Cryptography, and Message Integrity and Message Authentication, and Security at the Network Layer: IPSec.
Abstract: This book includes the following chapters : Introduction; Mathematics of Cryptography; Traditional Symmetric-Key Ciphers; Mathematics of Cryptography; Introduction to Modern Symmetric-Key Ciphers; Data Encryption Standard (DES); Advanced Encryption Standard (AES); Encipherment Using Modern Symmetric-Key Ciphers; Mathematics of Cryptography; Asymmetric-Key Cryptography; Message Integrity and Message Authentication; Cryptographic Hash Functions; Digital Signature; Entity Authentication; Key Management; Security at the Application Layer: PGP and S/MIME; Security at the Transport Layer: SSL and TLS; and Security at the Network Layer: IPSec.
854 citations
TL;DR: The simulation results demonstrate that the proposed method can significantly increase Trojan activity and reduce Trojan activation time and the relation between circuit topology, authentication time, and the threshold is carefully studied.
Abstract: Fabless semiconductor industry and government agencies have raised serious concerns about tampering with inserting hardware Trojans in an integrated circuit supply chain in recent years. Most of the recently proposed Trojan detection methods are based on Trojan activation to observe either a faulty output or measurable abnormality on side-channel signals. Time to activate a hardware Trojan circuit is a major concern from the authentication standpoint. This paper analyzes time to generate a transition in functional Trojans. Transition is modeled by geometric distribution and the number of clock cycles required to generate a transition is estimated. Furthermore, a dummy scan flip-flop insertion procedure is proposed aiming at decreasing transition generation time. The procedure increases transition probabilities of nets beyond a specific threshold. The relation between circuit topology, authentication time, and the threshold is carefully studied. The simulation results on s38417 benchmark circuit demonstrate that, with a negligible area overhead, our proposed method can significantly increase Trojan activity and reduce Trojan activation time.
260 citations
"Analysis of Secret Key Revealing Tr..." refers methods in this paper
...A technique for improving hardware trojan detection and reducing trojan activation time is proposed in [8] as time to activate a hardware trojan circuit is a major concern from the authentication viewpoint....
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TL;DR: A novel noninvasive, multiple-parameter side-channel analysisbased Trojan detection approach that uses the intrinsic relationship between dynamic current and maximum operating frequency of a circuit to isolate the effect of a Trojan circuit from process noise.
Abstract: Hardware Trojan attack in the form of malicious modification of a design has emerged as a major security threat. Sidechannel analysis has been investigated as an alternative to conventional logic testing to detect the presence of hardware Trojans. However, these techniques suffer from decreased sensitivity toward small Trojans, especially because of the large process variations present in modern nanometer technologies. In this paper, we propose a novel noninvasive, multiple-parameter side-channel analysisbased Trojan detection approach. We use the intrinsic relationship between dynamic current and maximum operating frequency of a circuit to isolate the effect of a Trojan circuit from process noise. We propose a vector generation approach and several design/test techniques to improve the detection sensitivity. Simulation results with two large circuits, a 32-bit integer execution unit (IEU) and a 128-bit advanced encryption standard (AES) cipher, show a detection resolution of 1.12 percent amidst ±20 percent parameter variations. The approach is also validated with experimental results. Finally, the use of a combined side-channel analysis and logic testing approach is shown to provide high overall detection coverage for hardware Trojan circuits of varying types and sizes.
207 citations
"Analysis of Secret Key Revealing Tr..." refers background or methods in this paper
...Combination of side channel analysis and logic testing approach to provide high overall detection coverage for hardware trojan circuits of varying types and sizes is also discussed in [9]....
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...A novel noninvasive, multiple-parameter side-channel analysis based trojan detection approach is discussed in [9] where the authors use an intrinsic relationship between dynamic current and maximum operating frequency of a circuit to isolate the effect of a trojan from process noise....
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