Analysis of THD and output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques

TLDR: In this paper, the authors have proposed three different carrier pulse width modulation techniques, which can reduce the total harmonic distortion and enhance the output voltages from a five level inverter, adopting the constant switching frequency, variable switching frequency (VSF), and phase shifted pulsewidth modulation (PSPWM) concepts.

Abstract: Multilevel inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter have several advantages such as lower total harmonic distortion (THD), lower electro magnetic interference (EMI) generation, high output voltage. The main feature of multilevel inverter is the ability to reduce the voltage stress on each power device due to the utilisation of multilevel on the DC bus. The advent of multilevel inverter topologies has caused variety of pulse width modulation strategies. In this paper, various carrier pulse width modulation techniques are proposed, which can minimise the total harmonic distortion and enhances the output voltages from five level inverter. Three methodologies adopting the constant switching frequency (CSF), variable switching frequency (VSF), and phase shifted pulse width modulation (PSPWM) concepts are proposed in this paper. The above methodologies divided into two techniques like subharmonic pulse width modulation which minimises total harmonic distortion and switching frequency optimal pulse width modulation which enhances the output voltages. Field programmable gate array (FPGA) has been chosen to implement the pulse width modulation due its fast proto typing, simple hardware and software design. The simulation and experimental results are presented.