Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator
26 May 2019-pp 1-5
TL;DR: The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method and the mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).
Abstract: This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an inverter based high-speed comparator, including the design of common-mode body biasing feedback circuitry. Both the main circuit and the supporting circuitry have been designed and implemented in a standard 28 nm CMOS technology with power supply of 0.9 V. The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method. The mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).
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01 Jan 2016
TL;DR: The logical effort designing fast cmos circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
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137 citations
12 Aug 2020
TL;DR: Two methods are presented, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittal matrix.
Abstract: This article presents two methods, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittance matrix. The proposed methods are used to develop a generalised two-port network analysis for the commonly used amplifier topologies, in the presence of the supply, ground, bulk, and input noise sources. Various illustrative case studies (common-source, common-gate, and push-pull amplifiers) are considered to validate the analytical method of different CMOS technology nodes (180 nm, 110 nm, and 28 nm) and foundries (Lfoundry, UMC, and TSMC). Both the proposed methods are compared with the relevant existing methods in terms of mean percentage error (MPE), and computational complexity. The mathematically derived expressions using two methods show less than 4% MPE when compared with the schematic simulation results, obtained by the SPICE based simulations. Also, the post-layout simulations (PLS) results for all the examples (designed in CMOS 180 nm Lfoundry technology) show excellent matching with schematic simulations. The proposed methods can be further applicable to antennas, complex circuits, digital circuits, etc.
6 citations
TL;DR: An encoder with majority-3 bubble error correction is used in the proposed ADC to reduce bubble errors and a temperature-compensated inverter-based comparator is proposed to reduce power consumption.
5 citations
TL;DR: The estimation-by-inspection method is extended to analyze the performance metrics of the AMS circuits and a speed-up factor of 9 has been achieved using the proposed method as compared to the EDA simulations.
Abstract: This paper presents the analysis of on-chip analog and mixed signal (AMS) circuits in the presence of supply noise, on- and off-chip interconnect effects. The estimation-by-inspection method is extended to analyze the performance metrics of the AMS circuits. For the purpose of validation, two different examples are considered, designed in UMC 130 nm and Lfoundry 180 nm technology-nodes. The mean percentage error (MPE) between electronic design automation (EDA) simulations and analytical results using the proposed method is less than 10% for various performance metrics of an AMS system. A speed-up factor of 9 has been achieved using the proposed method as compared to the EDA simulations.
2 citations
01 Oct 2020
TL;DR: The paper presents power supply induced jitter (PSIJ) analysis of a latch based differential CMOS bootstrapped driver, designed for radiation hard particle detection application and shows a good matching with the simulation and exhibits 13% of mean percentage error (MPE).
Abstract: The paper presents power supply induced jitter (PSIJ) analysis of a latch based differential CMOS bootstrapped driver, designed for radiation hard particle detection application. The energy efficient driver circuit consists of bootstrap capacitor, boosted node voltages and reduced number of transistors to enhance the gate voltage for better driving efficiency. The closed-form transfer function of the design is derived to analyse the PSIJ. The circuit has been designed in a 180 nm silicon-on-insulator (SOI) technology for its inherent radiation hard by design (RHBD) characteristics with V DD of 0.9 V and input frequency of 40 MHz. The worst case PSIJ of the driver circuit is 1.65 ps with ±10% of supply fluctuations. The mathematical model for the design shows a good matching with the simulation and exhibits 13% of mean percentage error (MPE).
References
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Book•
31 Aug 1983
TL;DR: Computer methods for circuit analysis and design, Computer methods forcircumference and design , مرکز فناوری اطلاعات و £1,000,000; اوشاوρزی £1,500,000.
Abstract: Computer methods for circuit analysis and design , Computer methods for circuit analysis and design , مرکز فناوری اطلاعات و اطلاع رسانی کشاورزی
1,144 citations
"Analysis of Timing Error Due to Sup..." refers methods in this paper
...The admittance matrix method [29] is one of the useful method to solve such a large number of circuit nodes and is thus used in the following subsection....
[...]
Book•
01 Jan 1999TL;DR: In this article, the authors derived the method of logical effort from design examples and calculated the logical effort of gates, and then calibrated the model to achieve equal rising and falling delays.
Abstract: 1 The Method of Logical Effort 2 Design Examples 3 Deriving the Method of Logical Effort 4 Calculating the Logical Effort of Gates 5 Calibrating the Model 6 Asymmetric Logic Gates 7 Unequal Rising and Falling Delays 8 Circuit Families 9 Forks of Amplifiers 10 Branches and Interconnect 11 Wide Structures 12 Conclusions A Cast of Characters B Reference process parameters C Logical Effort Tools D Solutions
646 citations
TL;DR: In this paper, operational transconductance amplifier (OTA) and filter design for analog circuits with very low supply voltages, down to 0.5 V, are presented. But they do not consider the effect of low-voltage analog circuits on the performance.
Abstract: We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.
471 citations
TL;DR: This brief reviews existing solutions to minimize the kickback noise and proposes two new ones and HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.
Abstract: The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.
324 citations
"Analysis of Timing Error Due to Sup..." refers background in this paper
...To improve the overall ADC performance, various static and dynamic comparators are reported in [8] [9]....
[...]
TL;DR: An analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived so that designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design.
Abstract: The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply.
318 citations