Analysis of Trace Levels of Ge Transferred to Si Wafer Surfaces during SiGe Wafer Processing
TL;DR: In this article, the effects of trace levels of Ge transferred to Si surfaces during thermal processing of SiGe wafers are presented in an oxidation furnace with SiGe relaxed graded buffer layers grown on Si.
Abstract: Effects of trace levels of Ge transferred to Si surfaces during thermal processing of SiGe wafers are presented here. Si wafers were coprocessed in an oxidation furnace with SiGe relaxed graded buffer layers grown on Si. Total X-ray fluorescence measurements on Si wafers showed Ge concentrations in varying degrees depending on oxidation temperature, time, and the number of coprocessed SiGe wafers. The Ge concentration level increases with increase of oxidation time, temperature, and SiGe wafer quantity. It was also observed that the furnace shows "memory" of the process during subsequent process runs. A chlorine-based purge of the oxidation tube after processing SiGe wafers helps reduce the Ge concentration remarkably. Metal oxide semiconductor capacitance and gate leakage characterization were used to evaluate the effects of transferred Ge on the gate oxide. The interface state density is marginally higher on Si wafers with transferred Ge.
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TL;DR: In this paper, the dependences of germanium incorporation in HfO 2 on dielectric deposition method, annealing temperature, and ambient were extensively studied by physical methods such as time-of-flight secondary ion mass spectroscopy.
Abstract: It is widely reported that a significant amount of germanium is incorporated in HfO 2 gate dielectric during the formation of high-K gate stack on germanium substrate. In this paper, the dependences of germanium incorporation in HfO 2 on dielectric deposition method, annealing temperature, and annealing ambient were extensively studied by physical methods such as time-of-flight secondary ion mass spectroscopy. The results indicate that the high thermal budget of processes, including deposition and annealing, is the most critical factor to the Ge incorporation. The Ge incorporation in HfO 2 is identified by two mechanisms: Ge atoms out-diffusion from substrate and gaseous GeO diffusion downward into HfO 2 via airborne transportation in the chamber.
26 citations
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TL;DR: In this paper, the authors studied the kinetics and mechanism of oxidation of SiGe alloys deposited epitaxially onto Si substrates by low-temperature chemical vapor deposition and demonstrated that Ge plays a purely catalytic role, i.e., it enhances the reaction rate while remaining unchanged itself.
Abstract: We have studied the kinetics and mechanism of oxidation of SiGe alloys deposited epitaxially onto Si substrates by low‐temperature chemical vapor deposition. Ge is shown to enhance oxidation rates by a factor of about 3 in the linear regime, and to be completely rejected from the oxide so that it piles up at the SiO2/SiGe interface. We demonstrate that Ge plays a purely catalytic role, i.e., it enhances the reaction rate while remaining unchanged itself. Electrical properties of the oxides formed under these conditions are presented, as well as microstructures of the oxide/substrate, Ge‐enriched/SiGe substrate, and SiGe/Si substrate interfaces, and x‐ray photoemission studies of the early stages of oxidation. Possible mechanisms are discussed and compared with oxidation of pure silicon.
315 citations
IBM1
TL;DR: In this paper, a 70% increase in electron mobility was observed at vertical fields as high as 1.5 MV/cm for the first time, suggesting a new mobility enhancement mechanism in addition to reduced phonon scattering.
Abstract: Performance enhancements in strained Si NMOSFETs were demonstrated at L/sub eff/<70 nm. A 70% increase in electron mobility was observed at vertical fields as high as 1.5 MV/cm for the first time, suggesting a new mobility enhancement mechanism in addition to reduced phonon scattering. Current drive increase by /spl ges/35% was observed at L/sub eff/<70 nm. These results indicate that strain can be used to improve CMOS device performance at sub-100 nm technology nodes.
179 citations
TL;DR: In this paper, the authors report on the recent developments and the performance level achieved in the strained-Si/SiGe material system, and propose possible future applications of strained Si and SiGe in high-performance SiGe CMOS technology.
Abstract: The purpose of this review article is to report on the recent developments and the performance level achieved in the strained-Si/SiGe material system. In the first part, the technology of the growth of a high-quality strained-Si layer on a relaxed, linear or step-graded SiGe buffer layer is reviewed. Characterization results of strained-Si films obtained with secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, spectroscopic ellipsometry and Raman spectroscopy are presented. Techniques for the determination of bandgap parameters from electrical characterization of metal-oxide-semiconductor (MOS) structures on strained-Si film are discussed. In the second part, processing issues of strained-Si films in conventional Si technology with low thermal budget are critically reviewed. Thermal and low-temperature microwave plasma oxidation and nitridation of strained-Si layers are discussed. Some recent results on contact metallization of strained-Si using Ti and Pt are presented. In the last part, device applications of strained Si with special emphasis on heterostructure metal oxide semiconductor field effect transistors and modulation-doped field effect transistors are discussed. Design aspects and simulation results of n- and p-MOS devices with a strained-Si channel are presented. Possible future applications of strained-Si/SiGe in high-performance SiGe CMOS technology are indicated.
178 citations
TL;DR: In this paper, a new high channel mobility strained-Si PMOSFET is presented, which is grown epitaxially on a completely relaxed step-graded Si/Si/SiO/sub 0.18/ buffer layer on Si(100) substrate.
Abstract: Operation and fabrication of a new high channel mobility strained-Si PMOSFET are presented. The growth of high-quality strained Si layer on completely relaxed, step-graded, SiGe buffer layer is demonstrated by gas source MBE. The strained-Si layer is characterized by double crystal X-ray diffraction, photoluminescence, and transmission electron microscopy. The operation of a PMOSFET is shown by device simulation and experiment. The high-mobility strained-Si PMOSFET is fabricated on strained-Si, which is grown epitaxially on a completely relaxed step-graded Si/sub 0.82/Ge/sub 0.18/ buffer layer on Si(100) substrate. At high vertical fields (high |V/sub g/|), the channel mobility of the strained-Si device is found to be 40% and 200% higher at 300 K and 77 K, respectively, compared to those of the bulk Si device. In the case of the strained-Si device, degradation of channel mobility due to Si/SiO/sub 2/ interface scattering is found to be more pronounced compared to that of the bulk Si device. Carrier confinement at the type-II strained-Si/SiGe-buffer interface is clearly demonstrated from device transconductance and C-V measurements at 300 K and 77 K.
163 citations
TL;DR: In this paper, the authors report on effective hole mobility in SiGe-based metal-oxide-semiconductor (MOS) field effect transistors grown by low-energy plasma-enhanced chemical vapor deposition.
Abstract: We report on effective hole mobility in SiGe-based metal–oxide–semiconductor (MOS) field-effect transistors grown by low-energy plasma-enhanced chemical vapor deposition The heterostructure layer stack consists of a strained Si017Ge083 alloy channel on a thick compositionally-graded Si052Ge048 buffer Structural assessment was done by high resolution x-ray diffraction Maximum effective hole mobilities of 760 and 4400 cm2/Vs have been measured at 300 and 77 K, respectively These values exceed the hole mobility in a conventional Si p-MOS device by a factor of 4 and reach the mobility data of conventional Si n-MOS transistors
126 citations