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Journal ArticleDOI

Analytic Estimation of Thermal Resistance in HBTs

TL;DR: In this paper, the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs) are estimated using the temperature dependence of thermal conductivity of the material.
Abstract: In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology.
Citations
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Journal ArticleDOI
TL;DR: In this article, an analytic model is proposed for estimating the junction temperature and thermal resistance in silicon-germanium heterojunction bipolar transistors (SiGe HBTs) including the back-end-of-line (BEOL) metal layers.
Abstract: An accurate analytic model is proposed for estimating the junction temperature and thermal resistance in silicon–germanium heterojunction bipolar transistors (SiGe HBTs) including the back-end-of-line (BEOL) metal layers. The model uses an average value of thermal conductivity in order to include the temperature dependence of thermal resistance. The parameters corresponding to the thermal conductivity and the BEOL thermal resistance used in the model are extracted following a recently reported methodology. The proposed model is scalable in nature and verification with experimental data shows an excellent accuracy across different emitter geometries of SiGe HBTs fabricated in STMicroelectronics B9MW technology. Compact model simulations show that the proposed model simulates around 23% faster compared with an existing state-of-the-art iterative method.

16 citations


Cites background or methods or result from "Analytic Estimation of Thermal Resi..."

  • ...The analytic results of T and RTH obtained for the proposed model in (9) are compared with the results of the analytic model in [6] for a different number of sections in Fig....

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  • ...In [6], it was reported that while using κ(Tavg) to obtain T and RTH, the accuracy increases with the reduction...

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  • ...However, in such approach, the accuracy of the results depends on the number of partitions in the entire heat flow volume [6]....

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  • ...For the first time, an interesting analytic model for RTH of SiGe HBTs was reported in [6] that is temperature-dependent and includes the effect of BEOL....

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  • ...In [6], it was shown that it is possible to obtain an analytic solution for the temperature-dependent RTH using the average temperature of each section....

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Journal ArticleDOI
TL;DR: In this paper, the contribution of the back-end-of-line (BEOL) layers on the thermal resistance of heterojunction bipolar transistors (HBTs) is analyzed.
Abstract: In this brief, we propose a simple approach to extract the contribution of the back-end-of-line (BEOL) layers on the thermal resistance of heterojunction bipolar transistors (HBTs). A finite value of BEOL thermal resistance obtained following our approach confirms a non-negligible heat flow toward BEOL. The proposed extraction technique is validated with iterative solutions and measured data of silicon–germanium HBTs fabricated in the STMicroelectronics B9MW technology.

13 citations


Cites background from "Analytic Estimation of Thermal Resi..."

  • ...where f (Gs) is the function of heat flow geometry in the semiconductor, which is independent of temperature and can be safely assumed to be constant for a given emitter geometry [6], [10]....

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  • ...To the best of our knowledge, an accurate estimate of the relative contributions of FEOL and BEOL on the overall thermal resistance is missing in the literature [6]....

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Journal ArticleDOI
TL;DR: In this article, the authors present and evaluate compact static thermal model parameter extraction techniques for modern silicon germanium heterojunction bipolar transistors (SiGe HBTs), which are primarily validated on SPICE generated synthetic data.
Abstract: In this article, we present and evaluate compact static thermal model parameter extraction techniques for modern silicon germanium heterojunction bipolar transistors (SiGe HBTs). We found that the model implementation of thermal resistance ( ${R}_{\text {th}}$ ) based on only junction temperature is implicit requiring time-consuming iterative procedure which may lead to potential instabilities. Dedicated extraction techniques are proposed for obtaining compact model-specific ${R}_{\text {th}}$ and its temperature coefficient. The proposed method is primarily validated on SPICE generated synthetic data. Next in order to showcase a compact model-independent verification, we also test the method using detailed thermal simulation from TCAD. Finally, we apply our extraction technique on measured data from fabricated transistors. The results are benchmarked to already obtained nominal ${R}_{\text {th}}$ values from the same device family.

9 citations


Cites background from "Analytic Estimation of Thermal Resi..."

  • ...Analytic thermal resistance estimation including temperature-dependent thermal conductance of Si was proposed in [14] and [15] for revealing the mechanisms of scaling exacerbated by the effect of shallow trench isolation (STI) and deep trench isolation (DTI) technologies....

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Proceedings ArticleDOI
18 Mar 2019
TL;DR: In this article, a thermal impedance model of single-finger and multi-finger SiGe heterojunction bipolar transistors (HBTs) is presented, where the heat flow analysis through the device has to be considered in two diffusion parts: the front-end-of-line (FEOL) diffusion and the back-end of line diffusion.
Abstract: A thermal impedance model of single-finger and multi-finger SiGe heterojunction bipolar transistors (HBTs) is presented. The heat flow analysis through the device has to be considered in two diffusion parts: the front-end-of-line (FEOL) diffusion and the back-end-of-line (BEOL) diffusion. Therefore, this new thermal impedance model features multi-poles network which has been incorporated in HiCuM L2 compact model. The HiCuM compact model simulation results are compared with on-wafer low-frequency S-parameters measurements at room temperature highlighting the device frequency dependence of self-heating mechanism. The simulation results are also compared to pulse measurements to improve reliability analysis.

9 citations


Cites background from "Analytic Estimation of Thermal Resi..."

  • ...For the rest of the paper, the heat diffusion angle θ is set to 45° as proposed in [9]....

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  • ...Front-end-of-line heat diffusion As presented in [9], the downward heat flow featuring a diffusion angle θ can be modeled by the superposition of N subsections leading to a distributed electro-thermal network....

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References
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Journal ArticleDOI
TL;DR: In this paper, a detailed review of a full SiGe HBT BiCMOS process is presented, with a description of a 12-bit Digital-to-Analog Converter.
Abstract: For pt. I, see ibid., vol. 3, p. 455-68 (1995). This part focuses on process integration concerns, first described in general terms and then detailed through an extensive review of both simple non-self-aligned device structures and more complex self-aligned device structures. The extension of SiGe device technology to high levels of integration is then discussed through a detailed review of a full SiGe HBT BiCMOS process. Finally, analog circuit design is discussed and concluded, with a description of a 12-bit Digital-to-Analog Converter presented to highlight the current status of SiGe technology. >

240 citations


"Analytic Estimation of Thermal Resi..." refers background in this paper

  • ...The scaled devices additionally use shallow trench isolation (STI) and deep trench isolation (DTI) to further enhance the performances by reducing the overall parasitic capacitances [4]....

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Journal ArticleDOI
R.C. Joy1, E.S. Schlig1
TL;DR: In this paper, a mathematical model of the three-dimensional transient heat flow problem is presented which takes into account the physical structure of the device and the actual region of power dissipation.
Abstract: Recent predictions that thermal effects will limit future transistor speed improvement motivated an interest in predicting and measuring these effects. A mathematical model of the three-dimensional transient heat flow problem is presented which takes into account the physical structure of the device and the actual region of power dissipation. At any point within the device, the model predicts the time-dependent temperature response to a change in power dissipation. A new method of measuring the local time-dependent thermal behavior of small bipolar transistors is described and used to verify the model. It was found that the thermal spreading resistance becomes important in silicon transistors when the emitter stripe dimensions approach 1 µ. Furthermore, the thermal response is much slower than the electrical response. Also, it was confirmed that adjacent devices in integrated circuits are essentially thermally isolated as far as thermal spreading resistance is concerned.

162 citations


"Analytic Estimation of Thermal Resi..." refers background in this paper

  • ...2572959 Starting from the widely known work of [9], significant efforts have been made to better understand the behavior of RTH for various technologies in the subsequent publications [10]–[12]....

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Journal ArticleDOI
TL;DR: In this article, the emitter ballasting resistor for power heterojunction bipolar transistors (HBTs) was investigated and the current handling capability of power HBTs was found to improve with ballasting resistance.
Abstract: A systematic investigation of the emitter ballasting resistor for power heterojunction bipolar transistors (HBTs) is presented. The current handling capability of power HBTs is found to improve with ballasting resistance. An equation for the optimal ballasting resistance is presented, where the effects of thermal conductivity of the substrate material and the temperature coefficient of the ballasting resistor are taken into account. Current levels of 400 to 800 mA/mm of emitter periphery at case temperatures of 25 to -80 degrees C for power AlGaAs/GaAs HBTs have been obtained using an on-chip lightly doped GaAs emitter ballasting resistor. Device temperature has been measured using both an infrared microradiometer and temperature-sensitive electrical parameters. Steady-state and transient thermal modeling are also performed. Although the measured temperature is spatially nonuniform, the modeling results show that such nonuniformities would occur for a uniform current distribution, as would be expected for an HBT with emitter ballasting resistors. >

122 citations


"Analytic Estimation of Thermal Resi..." refers background in this paper

  • ...where f (WE , L E , h, θ) is expressed as [15]...

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Book
25 Nov 2010
TL;DR: This book begins with an overview on the different device designs of modern bipolar transistors, along with their relevant operating conditions; while the subsequent chapter on transistor theory is subdivided into a review of mostly classical theories, brought into context with modern technology.
Abstract: "Compact Hierarchical Bipolar Transistor Modeling with HICUM" will be of great practical benefit to professionals from the process development, modeling and circuit design community who are interested in the application of bipolar transistors, which include the SiGe:C HBTs fabricated with existing cutting-edge process technology. This book begins with an overview on the different device designs of modern bipolar transistors, along with their relevant operating conditions; while the subsequent chapter on transistor theory is subdivided into a review of mostly classical theories, brought into context with modern technology, and a chapter on advanced theory that is required for understanding modern device designs. This book aims to provide a solid basis for the understanding of modern compact models.

116 citations


"Analytic Estimation of Thermal Resi..." refers methods in this paper

  • ...An accurate estimation of RTH is useful from the perspectives of both device design and compact modeling [7]....

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Proceedings ArticleDOI
18 Nov 2011
TL;DR: In this paper, the authors summarized the technological developments carried out on SiGe HBTs in the frame of the European project DOTFIVE and discussed the architectures of the different partners and their performances.
Abstract: This paper summarizes the technological developments carried out on SiGe HBTs in the frame of the European project DOTFIVE. The architectures of the different partners and their performances are presented and discussed showing that the project objectives have been met.

102 citations


"Analytic Estimation of Thermal Resi..." refers background in this paper

  • ...AGGRESSIVELY scaled modern silicon germanium heterojunction bipolar transistors (SiGe HBTs) offer subterahertz operation capabilities [1], [2]....

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Trending Questions (1)
How can we prevent thermal runaway in transistors?

This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors.