Analytical Approximation of Quantum Mechanical Tunneling and Characterization of Nano-Scale Heterojunction Double Gate Tunnel FETs
01 Jul 2019-
TL;DR: In this article, the analytical models of quantum mechanical tunneling concepts are discussed and the performance of DG TFETs with gate-drain overlap is analyzed using different materials such as Si, SiGe, InAs and GaSb.
Abstract: In this paper the analytical models of quantum mechanical tunneling concepts are discussed. Double gate (DG) tunnel field effect transistors (TFETs) with gate-drain overlap have been proposed from the perspective of improving the device performance in terms of the drive current (I ON ). In the gate-drain overlap region, an asymmetric gate oxide is introduced and compared to that of DG TFET without overlap. The physics and performance of the devices are analyzed using different materials such as Si, SiGe, InAs and GaSb. Higher tunneling probability is observed for DG TFETs with gate-drain overlap compared to that of DG TFETs without overlap. Furthermore, GaSb based DG TFETs have shown an excellent improvement in the device performance by offering high I ON of 1.15 mA/µm.
References
More filters
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.
1,230 citations
"Analytical Approximation of Quantum..." refers background in this paper
...A number of quantitative benchmarking results indicate that some emerging devices, for example, Tunnel Field Effect Transistors (TFETs), may accomplish to lower switching energy than the current CMOS, exhibiting their capability to be utilized in future electronic circuits [2], [3]....
[...]
TL;DR: In this paper, a dual material gate (DMG) was applied to a tunnel field effect transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage.
Abstract: In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.
382 citations
"Analytical Approximation of Quantum..." refers background in this paper
...As TFETs operates at SS below 60 mV/dec, it offers higher ION/IOFF ratio at decreased supply voltages therefore empowering forceful supply voltage scaling [9], [10]....
[...]
TL;DR: In this article, a Si nanowire based tunneling field effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure has been presented.
Abstract: This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion/Ioff ratio (105), as well as low Drain-Induced Barrier Lowering of 70 mV/V.
297 citations
TL;DR: In this article, the authors demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET).
Abstract: In this paper, we have demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET). Unlike in the conventional TFET where the gate controls the tunneling barrier width at both source-channel and channel-drain interfaces for different polarity of gate voltage, overlapping the gate on the drain limits the gate to control only the tunneling barrier width at the source-channel interface irrespective of the polarity of the gate voltage. As a result, the proposed overlapping gate-on-drain TFET exhibits suppressed ambipolar conduction even when the drain doping is as high as \(1 \times 10^{19}\) cm \(^{-3}\) .
251 citations
TL;DR: In this article, an L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for the first time.
Abstract: An L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for the first time. It is more scalable than other vertical-BTBT-based TFET designs and provides more than $1000\times $ higher ON-current ( $I_{{\mathrm{\scriptscriptstyle ON}}}$ ) than a conventional planar TFET with the same gate overdrive ( $V_{\mathrm{ov}}$ ) of 0.8 V, due to improved subthreshold swing ( $S$ ) and larger tunnel junction area. Its temperature dependence, constant $S$ , and nonlinear output characteristics are discussed.
226 citations