Analytical Design and Simulation Studies of Super-junction Power MOSFET

Strengthen Anti-ESD Characteristics in an HV LDMOS With Superjunction Structures

Abstract: In general, the antielectrostatic discharge (ESD) ability of a high voltage (HV) MOSFET device will be very low if it is not optimized through the addition of reliability engineering. Accordingly, in this paper, some embedded superjunction (SJ) device under tests (DUTs) of 45-V HV n-channel lateral-diffused MOS (nLDMOS) are developed, which offer a low on-resistance as compared with the traditional nLDMOS due to the redistribution of electric field or/and higher doping density in the drain side. In order to evaluate how various physical parameters affect the anti-ESD capability, these DUTs will change the widths and shapes of the P/N pillars. From the testing results, it can be found that the I t2 values of SJ-nLDMOS DUTs will be higher than that of a traditional nLDMOS, while the equivalent immunity level is even greater than HBM 10 kV. In this paper, the I t2 values of developed SJ-nLDMOS DUTs were increased at least by 109%, 31%, and 159% over that of the traditional nLDMOS for the Types 1-3 embedded SJ, respectively. Moreover, in some geometry architectures of an SJ-LDMOS, the holding voltage can be greater than the traditional nLDMOS. Therefore, by considering the relationships between these three kinds of SJ-nLDMOS DUTs and the I t2 values, it can be determined that the SJ structure is good for ESD/latch-up immunities especially for the ESD reliability.

Towards reduced threshold voltages for vertical power Mosfet transistors

Abstract: The threshold voltage of insulated gate power transistors usually is around 3 to 4V and their nominal gate to source voltage between 15 and 20V. These unanimously recognized electrical characteristics are questioned in this paper in order to evaluate which benefits could be drawn from a reduction of the threshold voltage of power transistors. Logic level MOSFETs already exist, but this paper chooses to study theoretically the electrical and physical characteristics of power transistors as a function of the threshold voltage to see if these electrical values of power electronics standards are still appropriate. It appears that the reduction of the threshold voltage of power MOSFET reduces the amount of control power and may improve switching characteristics.

COOLMOS/sup TM/-a new milestone in high voltage power MOS

Abstract: Recently, a new technology for high voltage power MOSFETs has been introduced: the CoolMOS/sup TM/. Based on the new device concept of charge compensation, the R/sub DS(on)/ area product for e.g. 600 V transistors has been reduced by a factor of 5. The devices show no bipolar current contribution like the well known tail current observed during the turn-off phase of IGBTs. CoolMOS/sup TM/ virtually combines the low switching losses of a MOSFET with the on-state losses of an IGBT. Furthermore, the dependence of R/sub DS(on)/ on the breakdown voltage has been redefined. The more than square-law dependence in the case of standard MOSFET has been broken and a linear voltage dependence achieved. This opens the way to new fields of application even without avalanche operation. System miniaturization, higher switching frequencies, lower circuit parasitics, higher efficiency, and reduced system costs are pointing the way towards future developments. Not only has the new technology achieved breakthrough at reduced R/sub DS(on)/ values, but new benchmarks have also been set for the device capacitances. Due to chip shrinkage and a novel internal structure, the technology shows both a very small input capacitance and a strongly nonlinear output capacitance. The drastically lower gate charge facilitates and reduces the cost of controllability, and the smaller feedback capacitance reduces the dynamic losses. With this new technology, the minimum R/sub DS(on)/ values in all packages are being redefined in the important 600-1000 V categories.

Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET

Abstract: In this paper, a novel device called the super junction MOSFET is analyzed using analytical modeling and numerical simulations. The effect of charge imbalance between the N and P pillars on the static and dynamic characteristics of the device is studied in detail. Simulations predict that this device is highly sensitive to charge imbalance if designed for optimum on-resistance. The breakdown voltage (BV) and E/sub off/ sensitivity can be reduced considerably by degrading the specific on-resistance R/sub on,sp/. The physics of the static and dynamic behaviour of this device under charge imbalance is explained with the help of numerical simulations.

Study of the quasi-saturation effect in VDMOS transistors

Abstract: The quasi-saturation effect in VDMOS transistors is studied in detail. It is shown that such behavior is due to carrier velocity saturation in the JFET region of the device. Two-dimensional numerical simulation is carried out to study the quasi-saturation effect and its relation to different device design parameters. Experimental results over a wide range of voltage and current levels are used to verify calculated dc characteristics. In addition, the design constraint on p-body spacing in order to avoid the quasi-saturation effect is defined.