Analytical Design and Simulation Studies of Super-junction Power MOSFET
04 Jun 2007-pp 503-508
TL;DR: Using the super-junction theory, an analytical design methodology for high voltage Super-Junction power MOSFET, which offers very low on resistance as compared with VDMOS power device due to higher doping density in the drift region, was developed in this paper.
Abstract: Using the super-junction theory we develop an analytical design methodology for high voltage Super-junction power MOSFET, which offers very low on resistance as compared with VDMOS power device due to higher doping density in the drift region. This method is used to analytically design various rating super-junction power MOSFET and using simulation tools, the validity of this method is established and then used to study the physical mechanisms underlying the device operation.
Citations
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TL;DR: In this article, an embedded superjunction (SJ) device under tests (DUTs) of 45-V HV n-channel lateral-diffused MOS (nLDMOS) is developed, which offer a low on-resistance as compared with the traditional nLDMos due to the redistribution of electric field or/and higher doping density in the drain side.
Abstract: In general, the antielectrostatic discharge (ESD) ability of a high voltage (HV) MOSFET device will be very low if it is not optimized through the addition of reliability engineering. Accordingly, in this paper, some embedded superjunction (SJ) device under tests (DUTs) of 45-V HV n-channel lateral-diffused MOS (nLDMOS) are developed, which offer a low on-resistance as compared with the traditional nLDMOS due to the redistribution of electric field or/and higher doping density in the drain side. In order to evaluate how various physical parameters affect the anti-ESD capability, these DUTs will change the widths and shapes of the P/N pillars. From the testing results, it can be found that the I
t2
values of SJ-nLDMOS DUTs will be higher than that of a traditional nLDMOS, while the equivalent immunity level is even greater than HBM 10 kV. In this paper, the I
t2
values of developed SJ-nLDMOS DUTs were increased at least by 109%, 31%, and 159% over that of the traditional nLDMOS for the Types 1-3 embedded SJ, respectively. Moreover, in some geometry architectures of an SJ-LDMOS, the holding voltage can be greater than the traditional nLDMOS. Therefore, by considering the relationships between these three kinds of SJ-nLDMOS DUTs and the I
t2
values, it can be determined that the SJ structure is good for ESD/latch-up immunities especially for the ESD reliability.
5 citations
27 Jun 2011
TL;DR: In this paper, the authors examined the electrical and physical characteristics of power transistors as a function of the threshold voltage to see if these electrical values of power electronics standards are still appropriate.
Abstract: The threshold voltage of insulated gate power transistors usually is around 3 to 4V and their nominal gate to source voltage between 15 and 20V. These unanimously recognized electrical characteristics are questioned in this paper in order to evaluate which benefits could be drawn from a reduction of the threshold voltage of power transistors. Logic level MOSFETs already exist, but this paper chooses to study theoretically the electrical and physical characteristics of power transistors as a function of the threshold voltage to see if these electrical values of power electronics standards are still appropriate. It appears that the reduction of the threshold voltage of power MOSFET reduces the amount of control power and may improve switching characteristics.
2 citations
References
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26 May 1999
TL;DR: The CoolMOS/sup TM/ as discussed by the authors, a new high voltage power MOSFET based on the concept of charge compensation, has been introduced, which shows both a very small input capacitance and a strongly nonlinear output capacitance.
Abstract: Recently, a new technology for high voltage power MOSFETs has been introduced: the CoolMOS/sup TM/. Based on the new device concept of charge compensation, the R/sub DS(on)/ area product for e.g. 600 V transistors has been reduced by a factor of 5. The devices show no bipolar current contribution like the well known tail current observed during the turn-off phase of IGBTs. CoolMOS/sup TM/ virtually combines the low switching losses of a MOSFET with the on-state losses of an IGBT. Furthermore, the dependence of R/sub DS(on)/ on the breakdown voltage has been redefined. The more than square-law dependence in the case of standard MOSFET has been broken and a linear voltage dependence achieved. This opens the way to new fields of application even without avalanche operation. System miniaturization, higher switching frequencies, lower circuit parasitics, higher efficiency, and reduced system costs are pointing the way towards future developments. Not only has the new technology achieved breakthrough at reduced R/sub DS(on)/ values, but new benchmarks have also been set for the device capacitances. Due to chip shrinkage and a novel internal structure, the technology shows both a very small input capacitance and a strongly nonlinear output capacitance. The drastically lower gate charge facilitates and reduces the cost of controllability, and the smaller feedback capacitance reduces the dynamic losses. With this new technology, the minimum R/sub DS(on)/ values in all packages are being redefined in the important 600-1000 V categories.
251 citations
26 May 1999
TL;DR: In this article, the effect of charge imbalance between the N and P pillars on the static and dynamic characteristics of the super junction MOSFET was studied in detail using analytical modeling and numerical simulations.
Abstract: In this paper, a novel device called the super junction MOSFET is analyzed using analytical modeling and numerical simulations. The effect of charge imbalance between the N and P pillars on the static and dynamic characteristics of the device is studied in detail. Simulations predict that this device is highly sensitive to charge imbalance if designed for optimum on-resistance. The breakdown voltage (BV) and E/sub off/ sensitivity can be reduced considerably by degrading the specific on-resistance R/sub on,sp/. The physics of the static and dynamic behaviour of this device under charge imbalance is explained with the help of numerical simulations.
213 citations
TL;DR: The Composite Buffer layer (CB-layer for short) as mentioned in this paper is a voltage-sustaining layer for power devices, which consists of alternating n- and p-type regions that are parallel to the direction of the applied electric field.
110 citations
"Analytical Design and Simulation St..." refers methods in this paper
...The SJ theory [ 2 ] gives analytical modeling of the SJ drift layer, where the doping profile of the SJ drift layer having p and n pillars has been modeled as a unitary function....
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