Analytical Design and Simulation Studies of Super-junction Power MOSFET
04 Jun 2007-pp 503-508
TL;DR: Using the super-junction theory, an analytical design methodology for high voltage Super-Junction power MOSFET, which offers very low on resistance as compared with VDMOS power device due to higher doping density in the drift region, was developed in this paper.
Abstract: Using the super-junction theory we develop an analytical design methodology for high voltage Super-junction power MOSFET, which offers very low on resistance as compared with VDMOS power device due to higher doping density in the drift region. This method is used to analytically design various rating super-junction power MOSFET and using simulation tools, the validity of this method is established and then used to study the physical mechanisms underlying the device operation.
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TL;DR: In this article, an embedded superjunction (SJ) device under tests (DUTs) of 45-V HV n-channel lateral-diffused MOS (nLDMOS) is developed, which offer a low on-resistance as compared with the traditional nLDMos due to the redistribution of electric field or/and higher doping density in the drain side.
Abstract: In general, the antielectrostatic discharge (ESD) ability of a high voltage (HV) MOSFET device will be very low if it is not optimized through the addition of reliability engineering. Accordingly, in this paper, some embedded superjunction (SJ) device under tests (DUTs) of 45-V HV n-channel lateral-diffused MOS (nLDMOS) are developed, which offer a low on-resistance as compared with the traditional nLDMOS due to the redistribution of electric field or/and higher doping density in the drain side. In order to evaluate how various physical parameters affect the anti-ESD capability, these DUTs will change the widths and shapes of the P/N pillars. From the testing results, it can be found that the I
t2
values of SJ-nLDMOS DUTs will be higher than that of a traditional nLDMOS, while the equivalent immunity level is even greater than HBM 10 kV. In this paper, the I
t2
values of developed SJ-nLDMOS DUTs were increased at least by 109%, 31%, and 159% over that of the traditional nLDMOS for the Types 1-3 embedded SJ, respectively. Moreover, in some geometry architectures of an SJ-LDMOS, the holding voltage can be greater than the traditional nLDMOS. Therefore, by considering the relationships between these three kinds of SJ-nLDMOS DUTs and the I
t2
values, it can be determined that the SJ structure is good for ESD/latch-up immunities especially for the ESD reliability.
5 citations
27 Jun 2011
TL;DR: In this paper, the authors examined the electrical and physical characteristics of power transistors as a function of the threshold voltage to see if these electrical values of power electronics standards are still appropriate.
Abstract: The threshold voltage of insulated gate power transistors usually is around 3 to 4V and their nominal gate to source voltage between 15 and 20V. These unanimously recognized electrical characteristics are questioned in this paper in order to evaluate which benefits could be drawn from a reduction of the threshold voltage of power transistors. Logic level MOSFETs already exist, but this paper chooses to study theoretically the electrical and physical characteristics of power transistors as a function of the threshold voltage to see if these electrical values of power electronics standards are still appropriate. It appears that the reduction of the threshold voltage of power MOSFET reduces the amount of control power and may improve switching characteristics.
2 citations
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TL;DR: In this article, the quasi-saturation effect in VDMOS transistors is studied in detail, and it is shown that such behavior is due to carrier velocity saturation in the JFET region of the device.
Abstract: The quasi-saturation effect in VDMOS transistors is studied in detail. It is shown that such behavior is due to carrier velocity saturation in the JFET region of the device. Two-dimensional numerical simulation is carried out to study the quasi-saturation effect and its relation to different device design parameters. Experimental results over a wide range of voltage and current levels are used to verify calculated dc characteristics. In addition, the design constraint on p-body spacing in order to avoid the quasi-saturation effect is defined.
103 citations
"Analytical Design and Simulation St..." refers background in this paper
...as tepi increases, The difference between simulated and analytical BV increases at higher thickness values due to analytical assumptions in design equations[ 6-8 ]....
[...]
...At Vgs=6V and 8V the conducting JFET region is pinched off near the top neck region and as gate voltage increases the JFET conducting region opens up for current flow and then accumulation region forms below the gate in the n column which helps in establishing a high drain current [ 6 ]...
[...]
...Finally, at about 30 V the drift velocity saturates [ 6 ] the small current increase in drain current beyond Vds=30 V is possible only by increasing the width of the conducting channel in the n pillar....
[...]
Journal Article•
TL;DR: In this paper, a super-junction (SJ) structure was designed for the lowest specific onresistance Ron, and the effect of varying the junction depth of a p-body/well and the cell pitch on the breakdown voltage was analyzed.
Abstract: In this research, we analytically designed a super-junction (SJ) structure and used a simulation tool to study its off-state charge imbalance behavior. In the case of a SJ MOSFET (CoolMOS), designed for the lowest specific onresistance Ron, the MOS part of the transistor (channel region) affected the symmetry, creating a charge imbalance; in addition to this, the imbalance in the SJ drift layer, which was inherently due to limitations in the fabrication process was simulated by varying the doping density of the pillars up to 10 %. The underlying physical mechanisms responsible for the reduction of the breakdown voltage (BV) were investigated in detail by using the electric field profiles and potential contours. The effect of varying the junction depth of a p-body/well and the cell pitch on the breakdown voltage was also analyzed. The trade off between BV sensitivity and specific Ron was also investigated.
16 citations
11 Sep 2001
TL;DR: In this article, the advantages and technological challenges of state-of-the-art power devices for fast switching applications are discussed, covering the power MOSFET, the high speed IGBT and the recently introduced compensation devices with 600 V blocking capability.
Abstract: This article focuses on the advantages and technological challenges of state-ofthe-art power devices for fast switching applications. It covers the power MOSFET, the high speed IGBT and the recently introduced compensation devices with 600 V blocking capability. Special emphasis is laid on the charge compensation
12 citations
"Analytical Design and Simulation St..." refers background in this paper
...as tepi increases, The difference between simulated and analytical BV increases at higher thickness values due to analytical assumptions in design equations[ 6-8 ]....
[...]
Journal Article•
7 citations