Analytical insight for CFG generation for Superscalar Simulator design for RISC architecture

TLDR: A initial phase of superscalar simulator design methodology of a MIPS RISC processor is described, which deals with the generation of control flow graph (CFG), after the compilation of the source text to the target code, and the complexities that arise when branch instructions containing delay slots occur in the code.

Abstract: A superscalar architecture is a form of MIMD based processor architecture which implements “Instruction Level Parallelism (ILP)” within a single processor. It's an enhanced type of parallelism, which allows several instructions to be issued and completed per clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor, in contrast to pipelining where several instructions are to be executed at the same time, but they have to be in different pipeline stages at a given moment. RISC has been adopted because of the simplicity of its uniform length instructions, better balancing of pipelining with more efficient execution. This paper describes a initial phase of superscalar simulator design methodology of a MIPS RISC processor. The present scope mainly deals with the generation of control flow graph (CFG), after the compilation of the source text to the target code, and the complexities that arise when branch instructions containing delay slots occur in the code. This paper gives an insight into the future challenges involved in Superscalar Simulator design.