Analytical Model for Drain Current of a Ballistic MOSFET
TL;DR: A simplified analytical approach within the framework of Landauer-Buttiker formalism has been employed to model the drain current in a ballistic n-channel MOSFET and the expression for the device threshold voltage has been obtained as mentioned in this paper.
Abstract: A simplified analytical approach within the framework of Landauer-Buttiker formalism has been employed to model the drain current in a ballistic n-channel metal oxide semiconductor field effect transistor (MOSFET) and the expression for the device threshold voltage has been obtained. To achieve ballistic operation the said MOSFET has been modeled considering low temperature (77 K) and intrinsic silicon channel for electronic motion of the charge carriers. The model incorporates quantum confinement effect, drain induced barrier lowering (DIBL) and short channel effects (SCE). Further, the effects due to surface scattering and back scattering are included in this model to obtain a near ballistic behavior. The current-voltage characteristics are compared with the available experimental results and are found to be in reasonable agreement.
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TL;DR: An analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) is introduced in this article.
Abstract: The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.
2 citations
Cites background from "Analytical Model for Drain Current ..."
...To overcome these issues, new novel device structures are introduced, such as multi-gate MOSFETs, which are classified as a double gate, Triple gate, and cylindrical surrounding gate [5-7]....
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TL;DR: In this article , a numerical compact model for describing the drain current in ballistic mode by using an expression to represent the transmission coefficients for all operating regions is proposed, based on the previous study of an analytic compact model.
Abstract: We propose a numerical compact model for describing the drain current in ballistic mode by using an expression to represent the transmission coefficients for all operating regions. This model is based on our previous study of an analytic compact model for the subthreshold region in which the DIBL and source-to-drain tunneling effects were both taken into account. This paper introduces an approach to establishing the smoothing function for expressing the critical parameters in the model’s overall operating regions. The resulting compact model was tested in a TCAD NEGF simulation, demonstrating good consistency.
1 citations
TL;DR: In this article , an analytical modeling framework was used to investigate the I-V characteristics of field-effect transistors based on MoS2, and the effect of phonon scattering on the device was examined by including transmission probabilities into the ballistic current equation.
Abstract: Molybdenum disulfide (MoS2) has distinctive electronic and mechanical properties which make it a highly prospective material for use as a channel in upcoming nanoelectronic devices. An analytical modeling framework was used to investigate the I–V characteristics of field-effect transistors based on MoS2. The study begins by developing a ballistic current equation using a circuit model with two contacts. The transmission probability, which considers both the acoustic and optical mean free path, is then derived. Next, the effect of phonon scattering on the device was examined by including transmission probabilities into the ballistic current equation. According to the findings, the presence of phonon scattering caused a decrease of 43.7% in the ballistic current of the device at room temperature when L = 10 nm. The influence of phonon scattering became more prominent as the temperature increased. In addition, this study also considers the impact of strain on the device. It is reported that applying compressive strain could increase the phonon scattering current by 13.3% at L = 10 nm at room temperature, as evaluated in terms of the electrons’ effective masses. However, the phonon scattering current decreased by 13.3% under the same condition due to the existence of tensile strain. Moreover, incorporating a high-k dielectric to mitigate the impact of scattering resulted in an even greater improvement in device performance. Specifically, at L = 6 nm, the ballistic current was surpassed by 58.4%. Furthermore, the study achieved SS = 68.2 mV/dec using Al2O3 and an on–off ratio of 7.75 × 104 using HfO2. Finally, the analytical results were validated with previous works, showing comparable agreement with the existing literature.
1 citations
References
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TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Abstract: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.
3,008 citations
IBM1
TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
1,417 citations
IBM1
TL;DR: In this article, self-consistent results for energy levels, populations, and charge distributions are given for $n$-type inversion layers on $p$ -type silicon.
Abstract: Self-consistent results for energy levels, populations, and charge distributions are given for $n$-type inversion layers on $p$-type silicon. Quantum effects are taken into account in the effective-mass approximation, and the envelope wave function is assumed to vanish at the surface. Approximate analytic results are given for some special cases. Numerical results are given for representative surface orientations, bulk acceptor concentrations, inversion-layer electron concentrations, and temperatures.
987 citations
"Analytical Model for Drain Current ..." refers background or methods in this paper
...The parameters, as shown in Table 1, are used throughout this work [33]....
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...At low temperatures, when only one sub-band is occupied, approximately 80% of the charge carriers are contributed from the lowest level [33]....
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Book•
17 Oct 2007
TL;DR: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FET) and explains the physics and properties.
Abstract: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.
843 citations
"Analytical Model for Drain Current ..." refers background in this paper
...These terms apart from other parameters depend on effective channel length and junction depth [35]....
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TL;DR: In this paper, numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors, and the model reduces to Natori's theory of the ballistic MOSFET.
Abstract: Numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors. When two-dimensional (2-D) electrostatic effects are small (and when the insulator capacitance is much less than the semiconductor (quantum) capacitance), the model reduces to Natori's theory of the ballistic MOSFET. The model also treats 2-D electrostatics and the quantum capacitance limit where the semiconductor quantum capacitance is much less than the insulator capacitance. This new model provides insights into the performance of MOSFETs near the scaling limit and a unified framework for assessing and comparing a variety of novel transistors.
740 citations
"Analytical Model for Drain Current ..." refers background in this paper
...[23] have presented a unified framework for assessing the performance limit of MOSFETs by properly treating two dimensional electrostatics in the quantum capacitance limit....
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