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Journal ArticleDOI

Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs

TL;DR: In this article, analytical models of sub-threshold current and slope for asymmetric four-terminal double-gate (DG) MOSFETs are presented, and the results of the models show excellent match with simulations using MEDICI.
Abstract: In this paper, analytical models of subthreshold current and slope for asymmetric four-terminal double-gate (DG) MOSFETs are presented. The models are used to study the subthreshold characteristics with asymmetry in gate oxide thickness, gate material work function, and gate voltage. A model for the subthreshold behavior of three-terminal DG MOSFETs is also presented. The results of the models show excellent match with simulations using MEDICI. The analytical models provide physical insight which is helpful for device design.
Citations
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Journal ArticleDOI
TL;DR: An analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time in this article, which explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation.
Abstract: Based on the bulk conduction mode of the quasi-2-D scaling theory, an analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation. The model can also be extended to modeling accumulation/inversion operation mode for JL/junction-based double-gate MOSFETs. The model is verified by 2-D device simulations and can be easily used to explore the threshold voltage behavior of the JL double-gate MOSFETs due to its simple formula and computational efficiency.

129 citations


Additional excerpts

  • ...According to previous references in the literature [20], [21], the effective channel length can be defined as...

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Journal ArticleDOI
Zhihao Ding1, Guangxi Hu1, Jinglun Gu1, Ran Liu1, Lingli Wang1, Tingao Tang1 
TL;DR: The results show the variation of channel potential and subthreshold swing with channel length, gate bias, and oxide thickness, which will provide some guidance for the integrated circuit designs.

64 citations


Cites methods from "Analytical Model of Subthreshold Cu..."

  • ...However, the model in [4] is only applicable to the 3-T symmetric DG MOSFETs, while the model in [5] does not predict the variation of S with doping density....

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  • ...Models for S based on evanescent method have been obtained [4,5]....

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Journal ArticleDOI
TL;DR: In this article, an analytical 2D model for the channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile was proposed.
Abstract: This paper proposes an analytical 2-D model for the channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile. The 2-D Poisson equation has been solved by using the evanescent-mode analysis to obtain the potential distribution function in the channel. The position of the conduction path also has been modeled to calculate the potential at different positions of the conduction path. The validity of the proposed 2-D potential and threshold voltage models is shown by comparing the results with the simulation data obtained by a 2-D TCAD ATLAS device simulator.

63 citations


Cites background from "Analytical Model of Subthreshold Cu..."

  • ...The effective conduction path in the channel is defined as the location x = xc, where the minimum potential function ψmin(x) has the maximum value [24]....

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Journal ArticleDOI
TL;DR: In this paper, a new nanoscale graded channel gate stack (GCGS) double-gate (DG) MOSFET structure and its 2-D analytical model have been proposed, investigated and expected to suppress the short-channel effects (SCEs) and improve the sub-threshold performances for nanoelectronics applications.
Abstract: In this paper, a new nanoscale graded channel gate stack (GCGS) double-gate (DG) MOSFET structure and its 2-D analytical model have been proposed, investigated and expected to suppress the short-channel-effects (SCEs) and improve the subthreshold performances for nanoelectronics applications. The model predicts a shift, increasing potential barrier, in the surface potential profile along the channel, which ensures a reduced threshold voltage roll-off and DIBL effects. In the proposed structure, the subthreshold current and subthreshold swing characteristics are greatly improved in comparison with the conventional DG MOSFETs. The developed approaches are verified and validated by the good agreement found with the numerical simulation. (GCGS) DG MOSFET can alleviate the critical problem and further improve the immunity of SCEs of CMOS-based devices in the nanoscale regime.

54 citations

Journal ArticleDOI
TL;DR: In this paper, a 10-nm Dual-Material Surrounded Gate MOSFETs (DMSG) was proposed and simulated for nanoscale digital circuit applications and the sub-threshold electrical properties such as subthreshold current-voltage characteristics, sub-reshold swing factor, threshold voltage and drain induced barrier lowering (DIBL) of the device have been ascertained and mathematical models have been developed.
Abstract: In this paper, we have proposed and simulated a new 10-nm Dual-Material Surrounded Gate MOSFETs (DMSG) MOSFETs for nanoscale digital circuit applications. The subthreshold electrical properties such as subthreshold current–voltage characteristics, subthreshold swing factor, threshold voltage and drain induced barrier lowering (DIBL) of the device have been ascertained and mathematical models have been developed. It has been observed that the DM design can effectively suppress short-channel effects as compared to single material gate structure. The proposed analytical expressions are used to formulate the objective functions, which are the pre-requisite of genetic algorithm computation. The problem is then presented as a multi-objective optimization one where the subthreshold electrical parameters are considered simultaneously. Therefore, the proposed technique is used to search of the optimal electrical and geometrical parameters to obtain better electrical performance of the 10-nm-scale transistor. These characteristics make the optimized 10-nm transistors potentially suitable for deep nanoscale logic and memory applications.

35 citations

References
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Journal ArticleDOI
TL;DR: In this article, the short channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation, and it is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions.
Abstract: The short-channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation. The calculated values agree well with the simulation results. It is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions. The short-channel effect can be significantly reduced by decreasing the silicon film thickness. >

789 citations


"Analytical Model of Subthreshold Cu..." refers methods in this paper

  • ...Two-dimensional (2-D) potential variation based on parabolic approximation [7] has been employed in a subthreshold-current model for fully depleted silicon-on-insulator (FDSOI) MOSFET [8]....

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Journal ArticleDOI
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Abstract: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion. This original method of transistor operation offers excellent device performance, in particular great increases in subthreshold slope, transconductance, and drain current. A simulation program and experiments on SIMOX structures are used to study the new device.

729 citations


"Analytical Model of Subthreshold Cu..." refers background in this paper

  • ...THE double-gate (DG) MOS technology has emerged as one of the most promising candidates to extend the CMOS beyond the scaling limit of conventional technology due to excellent control of short-channel effects (SCEs) [1], [2]....

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Journal ArticleDOI
TL;DR: In this article, a continuous analytic currentvoltage model for double-gate MOSFETs is presented, which is derived from closed-form solutions of Poisson's equation, and current continuity equation without the charge-sheet approximation.
Abstract: This letter presents a continuous analytic current-voltage (I-V) model for double-gate (DG) MOSFETs. It is derived from closed-form solutions of Poisson's equation, and current continuity equation without the charge-sheet approximation. The entire I/sub ds/(V/sub g/,V/sub ds/) characteristics for all regions of MOSFET operation: linear, saturation, and subthreshold, are covered under one continuous function, making it ideally suited for compact modeling. By preserving the proper physics, this model readily depicts "volume inversion" in symmetric DG MOSFETs-a distinctively noncharge-sheet phenomenon that cannot be reproduced by standard charge-sheet based I-V models. It is shown that the I-V curves generated by the analytic model are in complete agreement with two-dimensional numerical simulation results for all ranges of gate and drain voltages.

361 citations


"Analytical Model of Subthreshold Cu..." refers background in this paper

  • ...THE double-gate (DG) MOS technology has emerged as one of the most promising candidates to extend the CMOS beyond the scaling limit of conventional technology due to excellent control of short-channel effects (SCEs) [1], [2]....

    [...]

Journal ArticleDOI
TL;DR: In this paper, a simple but powerful evanescent-mode analysis showed that the length /spl lambda/ over which the source and drain perturb the channel potential, is 1/spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the cylindrical case, in excellent agreement with PADRE device simulations.
Abstract: Short-channel effects in fully-depleted double-gate (DG) and cylindrical, surrounding-gate (Cyl) MOSFETs are governed by the electrostatic potential as confined by the gates, and thus by the device dimensions. The simple but powerful evanescent-mode analysis shows that the length /spl lambda/, over which the source and drain perturb the channel potential, is 1//spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the effective diameter in the cylindrical case, in excellent agreement with PADRE device simulations. Thus for equivalent silicon and gate oxide thicknesses, evanescent-mode analysis indicates that Cyl-MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs.

355 citations


"Analytical Model of Subthreshold Cu..." refers background or methods in this paper

  • ...As mentioned earlier, to solve the 2-D Poisson’s equation, we follow the evanescent method [10]....

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  • ...[9] has been shown to be superior [10]....

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Journal ArticleDOI
TL;DR: In this paper, the authors derived a new scale length for two-dimensional effects in MOSFETs and discussed its significance, and showed that the utility of higher dielectric constant gate insulators decreases for /spl epsiv/expexp/exp/spl/exp eps/exp v/expv//sub 0/>-20 and that in no event should the insulator be thicker than the Si depletion depth.
Abstract: We derive a new scale length for two-dimensional (2-D) effects in MOSFETs and discuss its significance. This derivation properly takes into account the difference in permittivity between the Si channel and the gate insulator, and thus permits an accurate understanding of the effects of using insufficiently scaled oxide or thicker higher permittivity gate insulators. The theory shows that the utility of higher dielectric constant insulators decreases for /spl epsiv///spl epsiv//sub 0/>-20, and that in no event should the insulator be thicker than the Si depletion depth. The approach is also applied to double-gated FET structures, resulting in a new more general scale length formula for them, too.

301 citations


"Analytical Model of Subthreshold Cu..." refers background in this paper

  • ...[9] has been shown to be superior [10]....

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  • ...Now, a general solution of (3) can be represented in Fourier series as [9]...

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