Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs
TL;DR: In this paper, a physically based model for the threshold voltage, subthreshold swing, and drain-induced barrier lowering (DIBL) of undoped cylindrical gate-all-around MOSFETs has been derived based on an analytical solution of 2-D Poisson's equation (in cylinrical coordinates) in which the mobile charge term has been included.
Abstract: Analytical physically based models for the threshold voltage, subthreshold swing, and drain-induced barrier lowering (DIBL) of undoped cylindrical gate-all-around MOSFETs have been derived based on an analytical solution of 2-D Poisson's equation (in cylindrical coordinates) in which the mobile charge term has been included. Using the new model, threshold voltage, DIBL and subthreshold swing sensitivities to channel length, and channel thickness have been investigated. The models for DIBL, subthreshold swing, and threshold voltage rolloff parameters have been verified by comparison with 3-D numerical simulations; close agreement with the numerical simulations has been observed
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TL;DR: In this article, the scaling of nanowire transistors to 10-nm gate lengths and below is considered and compared with the published experimental data of nan-wire transistors, and the performance limit of a nan-ire transistor is assessed by applying a ballistic current model.
Abstract: This paper considers the scaling of nanowire transistors to 10-nm gate lengths and below. The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first, yielding a general guideline between the gate length and the nanowire size for acceptable short-channel effects. Quantum confinement of electrons in the nanowire is discussed next. It gives rise to a ground-state energy and, therefore, a threshold voltage dependent on the radius of the nanowire. The scaling limit of nanowire transistors hinges on how precise the nanowire size can be controlled. The performance limit of a nanowire transistor is then assessed by applying a ballistic current model. Key issues such as the density of states of the nanowire material are discussed. Comparisons are made between the model results and the published experimental data of nanowire devices.
138 citations
Cites background from "Analytical Model of the Threshold V..."
...Another approach [22], [23] does not assume the parabolic potential profile but still uses 1-D Poisson’s equation in the insulator region....
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TL;DR: In this article, a 2D analytical model for the Dual Material Surrounding Gate MOSFET (DMSG) by solving the Poisson equation has been proposed and verified using ATLAS TCAD device simulator.
84 citations
TL;DR: An analytical physically based analysis for undoped FinFET devices in the subthreshold and near-threshold regimes has been developed by solving the 3-D Poisson equation, in which the mobile-charge term was included as mentioned in this paper.
Abstract: An analytical physically based analysis for undoped FinFET devices in the subthreshold and near-threshold regimes has been developed by solving the 3-D Poisson equation, in which the mobile-charge term was included. From this analysis, a subthreshold-swing model has been developed; this model is also based on a new physically based analysis of the conduction path. The subthreshold-swing model has been verified by comparison with 3-D numerical simulations and measured values; a very good agreement with both 3-D numerical simulation and the experimental results was observed.
57 citations
TL;DR: In this paper, a conformal mapping analysis of the potential distribution in the device body arising from the interelectrode capacitive coupling, combined with a self-consistent procedure to include the effects of the inversion charge is presented.
Abstract: A precise modeling framework for short-channel nanoscale double-gate (DG) and gate-all-around (GAA) MOSFETs is presented. For the DG MOSFET, the modeling is based on a conformal mapping analysis of the potential distribution in the device body arising from the interelectrode capacitive coupling, combined with a self-consistent procedure to include the effects of the inversion charge. The DG interelectrode coupling, which dominates the subthreshold behavior of the device, can also be applied with a high degree of precision to the cylindrical GAA MOSFET by performing a simple geometric scaling transformation to account for the difference in gate control in the two devices. Near threshold, self-consistent procedures invoking Poisson's equation in combination with boundary conditions and suitable modeling expressions for the potential are applied to the two devices. In strong inversion, these solutions converge to those of the respective long-channel devices. The drain current is calculated as part of the self-consistent treatment. The results for both the electrostatics and the current are in excellent agreement with numerical simulations.
53 citations
Cites methods from "Analytical Model of the Threshold V..."
...One possibility is to solve Laplace’s equation in cylindrical coordinates by means of a series expansion in Bessel functions [20]....
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TL;DR: In this paper, a fully analytical potential model, valid in the weak inversion regime of short-channel cylindrical gate-all-around (GAA) MOSFETs, is proposed.
Abstract: A fully analytical potential model, valid in the weak inversion regime of short-channel cylindrical gate-all-around (GAA) MOSFET, is proposed. The model derivation is based on a previous analytical expression for tetragonal GAA MOSFET and the rotational symmetry of the tetragonal cross section. Device simulations were performed to verify that the potential distribution along the channel is properly described in all positions within the silicon body. Using the potential model, analytical expressions for the threshold voltage, subthreshold swing and drain-induced barrier lowering have been derived. Including the short-channel effects within an existing model for the subthreshold leakage current and an analytical drain current model of long-channel devices in strong inversion, a compact drain current model has been derived describing with good accuracy the transfer and output characteristics of short-channel GAA MOSFETs in all regions of operation.
51 citations
References
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TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.
551 citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
477 citations
TL;DR: In this paper, a simple but powerful evanescent-mode analysis showed that the length /spl lambda/ over which the source and drain perturb the channel potential, is 1/spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the cylindrical case, in excellent agreement with PADRE device simulations.
Abstract: Short-channel effects in fully-depleted double-gate (DG) and cylindrical, surrounding-gate (Cyl) MOSFETs are governed by the electrostatic potential as confined by the gates, and thus by the device dimensions. The simple but powerful evanescent-mode analysis shows that the length /spl lambda/, over which the source and drain perturb the channel potential, is 1//spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the effective diameter in the cylindrical case, in excellent agreement with PADRE device simulations. Thus for equivalent silicon and gate oxide thicknesses, evanescent-mode analysis indicates that Cyl-MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs.
355 citations
IBM1
TL;DR: In this paper, a 1D analytical solution for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poisson's equation was derived, giving closed forms of band bending and volume inversion as a function of silicon thickness and gate voltage.
Abstract: A one-dimensional (1-D) analytical solution is derived for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution gives closed forms of band bending and volume inversion as a function of silicon thickness and gate voltage. A threshold criterion is derived which serves to quantify the gate work function requirements for a double-gate CMOS.
333 citations
"Analytical Model of the Threshold V..." refers background in this paper
...where φ is the electrostatic potential referred to the Fermi level in the source [17], [19], [20], and the electron density is given as...
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TL;DR: In this article, a theoretical description of the dependence of the threshold voltage, V/sub TH/, of SOI MOSFETs on a wide range to top silicon layer thickness, t/sub s/, using both classical and quantum-mechanical methods.
Abstract: A theoretical description is given of the dependence of the threshold voltage, V/sub TH/, of SOI MOSFETs on a wide range to top silicon layer thickness, t/sub s/, using both classical and quantum-mechanical methods. The quantum-mechanical effects become remarkable below the critical thickness and raise V/sub TH/ with decreasing t/sub s/. The classical method cannot be applied in such a thin t/sub s/ region, since classically obtained V/sub TH/ decreases monotonously with decreasing t/sub s/ even below the critical thickness. As a result, the V/sub TH/ curve as a function of t/sub s/ can be divided into two regions with a boundary at a critical t/sub s/, and the classical method can be applied above that critical thickness. >
242 citations