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Journal ArticleDOI

Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model

20 Mar 2015-IEEE Journal of the Electron Devices Society (Institute of Electrical and Electronics Engineers Inc.)-Vol. 3, Iss: 3, pp 240-243
TL;DR: In this article, an analytical model of threshold voltage for bulk MOSFETs is developed, which is derived from the physical charge-based core of BSIM6 model, taking into account short channel effects, and is used in commercial SPICE simulators for operating point information.
Abstract: In this paper, an analytical model of threshold voltage for bulk MOSFET is developed. The model is derived from the physical charge-based core of BSIM6 MOSFET model, taking into account short channel effects, and is intended to be used in commercial SPICE simulators for operating point information. The model is validated with measurement data from IBM 90-nm technology node using various popular threshold voltage extraction techniques, and good agreement is obtained.
Citations
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Journal ArticleDOI
TL;DR: In this article, a BSIM-based compact model for a high-voltage MOSFET is presented, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect.
Abstract: A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90-V LDMOS and 40-V VDMOS transistors, and shows excellent agreement.

23 citations

Journal ArticleDOI
TL;DR: An improved analytical model for flicker noise in MOSFETs is presented in this paper, which captures the effect of high-trap density in the halo regions of the devices.
Abstract: An improved analytical model for flicker noise (1/ $f$ noise) in MOSFETs is presented. Current models do not capture the effect of high-trap density in the halo regions of the devices, which leads to significantly different bias dependence of flicker noise across device geometry. The proposed model is the first compact model implementation capturing such effect and show distinct improvements over other existing noise models. The model is compatible with BSIM6, the latest industry standard model for bulk MOSFET, and is validated with measurements from 45-nm low-power CMOS technology node.

21 citations

Journal ArticleDOI
TL;DR: In this article, a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation is presented, which takes drain-to-source voltage, gate-tosource voltage and gate length into account.
Abstract: We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source–drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage ( $V_{\mathrm{ DS}})$ , gate-to-source voltage ( $V_{\mathrm{ GS}})$ , gate length ( $L_{G})$ , substrate doping concentration ( $N_{\mathrm{ sub}})$ , and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data.

15 citations


Cites methods from "Analytical Modeling and Experimenta..."

  • ...The threshold voltage (VTH) will be automatically calculated by BSIM6 model [18]....

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Journal ArticleDOI
TL;DR: An analytical model, based on the equivalent conductance of the halo device, is developed to understand the anomalous behavior of transconductance in halo implanted MOSFET for linear and saturation regions across both gate and body biases.
Abstract: In this paper, we report anomalous behavior of transconductance ( ${g}_{m}$ ) in halo implanted MOSFET for linear and saturation regions across both gate and body biases. The ${g}_{m}$ characteristics undergo sharp change of slope in saturation which cannot be modeled by conventional compact models. The cause of such behavior is identified and explained using the TCAD simulations of source side halo, drain side halo (DH), both side halos, and uniformly doped transistors. An analytical model, based on the equivalent conductance of the halo device, is developed to understand the ${g}_{m}$ behavior. It is shown that the commonly used approach where only the DH region is considered in saturation, is insufficient to model the atypical ${g}_{m}$ behavior. The effect of oxide thickness ( ${T}_{\text {ox}}$ ) variation on ${g}_{m}$ is also studied, which demonstrates a deviation from the conventional $g_{m}$ behavior for halo implanted devices with thicker ${T}_{\text {ox}}$ . A computationally efficient SPICE model is proposed to model ${g}_{m}$ characteristics which shows excellent matching with the measured data.

15 citations


Cites background from "Analytical Modeling and Experimenta..."

  • ...5 [13], where q is a normalized unitless quantity [8])....

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Journal ArticleDOI
TL;DR: In this paper, an analytical model that accurately captures anomalous matching characteristics of drain current in a halo-implanted MOSFET across bias, geometry, and temperature is presented.
Abstract: We present an analytical model that accurately captures anomalous matching characteristics of drain current in a halo-implanted MOSFET across bias, geometry, and temperature. It is shown that the variation in drain current in different gate bias regimes results from the random-dopant fluctuations (RDFs) in different spatial regions across the channel of the device with nonuniform channel doping. Such effects cannot be captured by existing compact models. Using the impedance field method to calculate the relative contributions of the RDF in the higher doped halo region and the lower doped channel region, we demonstrate, for the first time, an analytical model that can successfully capture the drain current mismatch from subthreshold to strong inversion. We also report for the first time the unique temperature dependence of matching of the drain current in halo-implanted devices and propose a model to capture this behavior. The model is validated using extensive technology computer-aided design analysis and experimental data and is can be extended to the framework of the industry standard BSIM-BULK (formerly BSIM6) MOS model.

13 citations


Cites methods from "Analytical Modeling and Experimenta..."

  • ...Note that VTH is defined here using the conventional max gm method [24], and since it is measured in the WI region, it is determined by the VTH of the halo region....

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References
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Book
01 Jan 1987
TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO-TERMINAL MOS STRUCTURE 3. THE THREE-TERMINAL MOS STRUCTURE 4. THE FOUR-TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION-IMPLANTED CHANNELS 6. SMALL-DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION - LARGE-SIGNAL MODELING 8. SMALL-SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH-FREQUENCY SMALL-SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION

3,156 citations


"Analytical Modeling and Experimenta..." refers background or methods in this paper

  • ...The drain current under the standard drift-diffusion formalism can be represented as [11],...

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  • ...The potential balance equation in conjunction with Poisson’s equation and Gauss’s law for the MOSFET is given as [11],...

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Journal ArticleDOI
TL;DR: Several of the extraction methods currently used to determine the value of threshold voltage from the measured drain current versus gate voltage transfer characteristics, focusing specially on single-crystal bulk MOSFETs are reviewed.

813 citations


"Analytical Modeling and Experimenta..." refers methods in this paper

  • ...There are several methods proposed in literature to extract threshold voltage [6]–[10]....

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Journal ArticleDOI
TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

466 citations

Journal ArticleDOI
TL;DR: In this article, the authors modify the Pao-Sah drain current model to incorporate a mobility model and obtain 3% accuracy from subthreshold to very strong inversion for a wide range of substrate biases.
Abstract: In this paper, we discuss the low-drain voltage transconductance behavior of the MOSFET due to surface mobility variation, interface states and small geometry, and its application in threshold voltage determination. We modify the Pao-Sah drain current model to incorporate a mobility model and obtain 3% accuracy from subthreshold to very strong inversion for a wide range of substrate biases. The effects of non-ideal scaling, finite inversion layer thickness, surface roughness mobility degradation under high normal electric fields and interface states on the transconductance behavior are discussed. We observe the peak transconductance increases with substrate bias in short-channel devices and decreases with substrate bias in long-channel devices. Finally, we show the threshold voltage can be determined from the gate voltage at which the rate of transconductance change ( ∂g m ∂V GS ) is a maximum. This threshold voltage is identifiable with a known band-bending (surface potential) of the substrate (φ s ⋍ 2φ F + V SB ) , from which the band-bending at all gate biases can be calculated. The transconductance change (TC) method is insensitive to device degradations (e.g. mobility, series resistance, hot-carrier) in contrast to the conventional method of linear extrapolation to zero drain current.

295 citations

Journal ArticleDOI
TL;DR: In this article, the implications of inversion charge linearization in compact MOS transistor modeling are discussed, and an improvement to the EKV charge-based model is proposed in the form of a more accurate charge-voltage relationship.
Abstract: In this paper, the implications of inversion charge linearization in compact MOS transistor modeling are discussed. The charge-sheet model provides the basic relation among inversion charge and applied potentials, via the implicit surface potential. A rigorous derivation of simpler relations among inversion charge and applied external potentials is provided, using the technique of inversion charge linearization versus surface potential. The new concept of the pinch-off surface potential and a new definition of the inversion charge linearization factor are introduced. In particular, we show that the EKV charge-based model can be considered as an approximation to the more general approach presented here. An improvement to the EKV charge-based model is proposed in the form of a more accurate charge–voltage relationship. This model is analyzed in detail and shows an excellent agreement with the charge sheet model. The normalization of voltages, current and charges, as motivated by the inversion charge linearization, results in a major simplification in compact modeling in static as well as non-quasi-static derivations.

131 citations


"Analytical Modeling and Experimenta..." refers background or methods in this paper

  • ...Defining threshold voltage as the gate voltage at which Idrift = Idiff , using charge linearization [2], [4] and normalizing the inversion charge density to −2nqCoxVt leads to qi = (1)2 , where qi represents the normalized inversion charge density....

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  • ...First, pinch-off potential corresponding to qs = (1)2 (represented as ψp,th) is calculated using the general relationship among qi, pinch off potential (ψp) and channel potential (vch) [2]...

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