Analytical yield prediction considering leakage/performance correlation
01 Sep 2006-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE)-Vol. 25, Iss: 9, pp 1685-1695
TL;DR: A new chip-level statistical method to estimate the total leakage current in the presence of within-die and die-to-die variability is presented and an integrated approach to accurately estimate the yield loss when both frequency and power limits are imposed on a design is presented.
Abstract: In addition to traditional constraints on frequency, leakage current has emerged as a stringent constraint in modern processor designs. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield prediction must consider the dependence of leakage current on frequency. In this paper, a new chip-level statistical method to estimate the total leakage current in the presence of within-die and die-to-die variability is presented. A closed-form equation for total chip leakage that models the dependence of the leakage current distribution on different process parameters is developed. The proposed analytical expression is obtained directly from pertinent design information and includes both subthreshold and gate leakage currents. Using this model, an integrated approach to accurately estimate the yield loss when both frequency and power limits are imposed on a design is then presented. The proposed method demonstrates the importance of considering both these limiting factors while calculating the yield of a lot
Citations
More filters
TL;DR: The most important unreliability effects in nanometer CMOS technologies are reviewed and transistor aging models, intended for accurate circuit simulation, are described and efficient methods for circuit reliability simulation and analysis are discussed.
Abstract: Integrated analog circuit design in nanometer CMOS technologies brings forth new and significant reliability challenges. Ever-increasing process variability effects and transistor wear-out phenomena such as BTI, hot carrier degradation and dielectric breakdown force designers to use large design margins and to increase the uncertainty on the circuit lifetime. To help designers to tackle these problems at design time (i.e., Design For Reliability, or DFR), accurate transistor aging models, efficient circuit reliability analysis methods and novel design techniques are needed. The paper overviews the current state of the art in DFR for analog circuits. The most important unreliability effects in nanometer CMOS technologies are reviewed and transistor aging models, intended for accurate circuit simulation, are described. Also, efficient methods for circuit reliability simulation and analysis are discussed. These methods can help designers to analyze their circuits and to identify weak spots. Finally, cost-effective design techniques for more resilient and self-healing analog circuits are studied.
74 citations
TL;DR: This paper discusses an efficient method to analyze the spatial and temporal reliability of analog and digital circuits based on a screening experimental design succeeded by a set of regression DoEs, resulting in a good speed-accuracy tradeoff with a nearly linear complexity for all circuits under test.
Abstract: This paper discusses an efficient method to analyze the spatial and temporal reliability of analog and digital circuits. First, a SPICE-based reliability simulator with automatic step-size control is proposed. Both hot carrier degradation and negative bias temperature instability are included in the simulator. Next, a method to analyze the interaction between process variability effects and circuit aging is introduced. This method is based on a screening experimental design (DoE) succeeded by a set of regression DoEs, resulting in a good speed-accuracy tradeoff with a nearly linear complexity for all circuits under test. Finally, based on the DoE analysis, a circuit response surface model (RSM) is derived. The RSM is used for further circuit reliability analysis such as circuit weak spot detection and yield calculation as a function of circuit lifetime. The proposed method is validated over a broad range of both analog and digital circuits. Yield simulation time is reduced with up to three orders of magnitude, when compared to standard Monte Carlo-based techniques and while still maintaining simulation accuracy.
45 citations
Cites background from "Analytical yield prediction conside..."
...Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org....
[...]
IBM1
TL;DR: A statistical technique of yield computation for different voltage binning schemes is proposed using results of statistical timing and variational power analysis and solves the problem of computing optimal supply voltages for a given binning scheme.
Abstract: Process variation is recognized as a major source of parametric yield loss, which occurs because a fraction of manufactured chips do not satisfy timing or power constraints. On the other hand, both chip performance and chip leakage power depend on supply voltage. This dependence can be used for converting the fraction of too slow or too leaky chips into good ones by adjusting their supply voltage. This technique is called voltage binning [4]. All the manufactured chips are divided into groups (bins) and each group is assigned its individual supply voltage. This paper proposes a statistical technique of yield computation for different voltage binning schemes using results of statistical timing and variational power analysis. The paper formulates and solves the problem of computing optimal supply voltages for a given binning scheme. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids General Terms Algorithms, Design, Theory
35 citations
Cites background from "Analytical yield prediction conside..."
...Higher supply voltage improves chip performance but increases both leakage and switching power [10]....
[...]
Patent•
IBM1
TL;DR: In this paper, a method for improving parametric chip yield of manufactured chips is provided. But the method is based on performance and power consumption of a plurality of manufactured chip subject to a given voltage binning scheme.
Abstract: Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.
31 citations
References
More filters
Book•
01 Jan 1965
TL;DR: This chapter discusses the concept of a Random Variable, the meaning of Probability, and the axioms of probability in terms of Markov Chains and Queueing Theory.
Abstract: Part 1 Probability and Random Variables 1 The Meaning of Probability 2 The Axioms of Probability 3 Repeated Trials 4 The Concept of a Random Variable 5 Functions of One Random Variable 6 Two Random Variables 7 Sequences of Random Variables 8 Statistics Part 2 Stochastic Processes 9 General Concepts 10 Random Walk and Other Applications 11 Spectral Representation 12 Spectral Estimation 13 Mean Square Estimation 14 Entropy 15 Markov Chains 16 Markov Processes and Queueing Theory
13,886 citations
6,899 citations
"Analytical yield prediction conside..." refers background in this paper
...To calculate the total subthreshold leakage for a chip, we need to add the leakages device by device, considering that each device has unique RVs Ll and Vl, while sharing the same RVs Lg and Vg with all other devices....
[...]
Book•
01 Jan 1979
TL;DR: An electromagnetic pulse counter having successively operable, contact-operating armatures that are movable to a rest position, an intermediate position and an active position between the main pole and the secondary pole of a magnetic circuit.
Abstract: An electromagnetic pulse counter having successively operable, contact-operating armatures. The armatures are movable to a rest position, an intermediate position and an active position between the main pole and the secondary pole of a magnetic circuit.
4,897 citations
"Analytical yield prediction conside..." refers methods in this paper
...Given a normal (Gaussian) RV X ∼ N(µx ,σ 2 x), the pdf of X is given by [ 17 ]...
[...]
...Consequently, we use the Central Limit theorem [ 17 ] to approximate the distribution of this sum by a single deterministic number....
[...]
02 Jun 2003
TL;DR: Process, voltage and temperature variations; and their impact on circuit and microarchitecture; and possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are presented.
Abstract: Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture. Possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are also presented.
1,503 citations
"Analytical yield prediction conside..." refers background in this paper
...However, it has been observed [6] that among the “good” chips that meet the performance constraint, a substantial number of chips dissipate very large amounts of leakage power and, thus, are unsuitable for commercial usage....
[...]
...Hence, considerable variability in chip-level leakage current can be expected and measured variations as high as 20× have been reported in literature [6]....
[...]