Analyzing Impact of NBTI and Time-Zero Variability on Dynamic SRAM Metrics
01 Dec 2018-
TL;DR: The impact of NBTI onCritical Read Stability and Critical Writeability and TWRITE are shown and dynamic metrics T and T are correlated with static metrics SVNM and BWTV respectively for worst-case use conditions.
Abstract: Critical Read Stability (T READ ) and Critical Writeability (T WRITE ) are two SRAM metrics which can characterize the dynamic behavior of read and write operations. In this paper, the impact of NBTI on T READ and T WRITE is shown. Worst-case use conditions are identified by varying the relative degradation of the two p-FETs. Monte-Carlo simulations using foundry models (High-k Metal Gate planar MOSFET) are performed to analyze time-zero variability for different use conditions. The dynamic metrics T READ and T WRITE are correlated with static metrics SVNM and BWTV respectively for worst-case use conditions. Degradation trend of T READ and T WRITE is then discussed for worst and symmetric NBTI degradation cases by varying ΔV TH .
Citations
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TL;DR: The work in this paper demonstrates the cumulative impact of process variability and Negative Bias Temperature Instability (NBTI) degradation on the dynamic metrics of the SRAM cell under varied temperature conditions.
Abstract: Continuous scaling of CMOS technology has led to reliability issues and process variability that affect the circuit performance of the SRAM cell. The dynamic behavior of SRAM cells are characterized by critical read-stability (Tread) and critical write-ability (Twrite) while the Static Noise Margins (SNMs) are deduced by the static metrics that are the key performance metrics. The work in this paper demonstrates the cumulative impact of process variability and Negative Bias Temperature Instability (NBTI) degradation on the dynamic metrics of the SRAM cell under varied temperature conditions. Degradation due to NBTI is incorporated by considering different activity factors (α) for the dynamic metrics. Time-zero or process variability is performed for fresh-case, symmetric and asymmetric degradation by Monte Carlo run simulations using foundry models in addition to examining the effect of correlation with their corresponding static metrics.
1 citations
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TL;DR: In this article, the authors investigated the combined effect of negative bias temperature instability (NBTI) and process variability on the performance of CMOS technology and found that it is highly susceptible to ageing effects.
Abstract: Advanced CMOS technology is highly susceptible to ageing effects such as negative bias temperature instability (NBTI) and process variability. This article focuses on investigating the ‘combined im...
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TL;DR: In this paper , the collective degradation impact of bias temperature instability (BTI) and hot carrier injection (HCI) due to aging in an adaptive exponential "integrate and fire" (I&F) model-based, neuromorphic neuron circuit is examined.
Abstract: Reliability aspects such as bias temperature instability (BTI) and hot carrier injection (HCI) affecting devices in advanced CMOS‐based technology have been the subject of active research in recent decades. Due to these reliability issues, various digital and analog circuits were investigated for degradation. However, circuit blocks like the neuron circuits of neuromorphic systems are not fully explored. This work is inclined toward examining the collective degradation impact of BTI and HCI due to aging in an adaptive exponential “integrate and fire” (I&F) model‐based, neuromorphic neuron circuit. Detailed degradation analysis of the stimulated neuron circuit aided in identifying possible mismatches/faults associated with neuron spikes. These factors could reduce the efficiency of the neuronal circuit by potentially affecting the transmission of information in a neuromorphic system. Various performance parameters were then derived to quantify the extent of circuit deterioration. The proposed reliability‐aware design aims to improve the circuit degradation through its effectiveness in alleviating the overall reliability impact. It demonstrates enhanced circuit operation in spike generation even after aging. The circuit performance is validated through simulations at “Time0” (pre‐degradation) and “Aged” (post‐degradation) neuron netlists, which is then compared with the proposed reliability‐aware circuit.
References
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TL;DR: A simple solution to recover the SNM of the SRAM cell using a data flipping technique is proposed and the results simulated on BPTM 70nm and 100nm technology are presented.
Abstract: Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in Static Noise Margin (SNM), which is a measure of the read stability of the 6-T SRAM cell has been estimated using Reaction-Diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed technique.
330 citations
"Analyzing Impact of NBTI and Time-Z..." refers background in this paper
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TL;DR: By reformulating the Reaction–Diffusion model in a particularly simple form, it is shown that these seven apparently contradictory features of NBTI actually reflect different facets of the same underlying physical mechanism.
Abstract: Negative bias temperature instability (NBTI) is a well-known reliability concern for PMOS transistors. We review the literature to find seven key experimental features of NBTI degradation. These features appear mutually inconsistent and have often defied easy interpretation. By reformulating the Reaction–Diffusion model in a particularly simple form, we show that these seven apparently contradictory features of NBTI actually reflect different facets of the same underlying physical mechanism.
266 citations
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TL;DR: In this article, different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data.
Abstract: Different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data. Models that focus exclusively on hole trapping in gate-insulator-process-related preexisting traps are found to be inconsistent with direct experimental evidence of interface trap generation. Models that focus exclusively on interface trap generation are incapable of predicting ultrafast measurement data. Models that assume strong correlation between interface trap generation and hole trapping in switching hole traps cannot simultaneously predict long-time dc stress, recovery, and ac stress and cannot estimate gate insulator process impact. Uncorrelated contributions from generation and recovery of interface traps, together with hole trapping and detrapping in preexisting and newly generated bulk insulator traps, are invoked to comprehensively predict dc stress and recovery, ac duty cycle and frequency, and gate insulator process impact of NBTI. The reaction-diffusion model can accurately predict generation and recovery of interface traps for different devices and experimental conditions. Hole trapping/detrapping is modeled using a two-level energy well model.
246 citations
"Analyzing Impact of NBTI and Time-Z..." refers background in this paper
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IBM1
TL;DR: In this paper, the local stochastic distributions of read, write and retention DC margins of 65nm PDSOI CMOS SRAM cells were measured and shown to be more fluctuation limited.
Abstract: Fundamental limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring the local stochastic distributions of read, write and retention DC margins of 65nm PDSOI CMOS SRAM cells DC measurements show, for the first time, the write operation to be more fluctuation limited Measurements also reveal fundamental insights into terminal voltage dependencies of the fluctuations of cell storage node voltages - observations that are engaged to increase cell immunity to fluctuations by several orders of magnitude by biasing the cell terminal voltages appropriately
184 citations
"Analyzing Impact of NBTI and Time-Z..." refers background in this paper
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TL;DR: This paper analyzes write ability for SRAM cells in deeply scaled technologies by considering the write operation as a noise event that is analyzed using dynamic stability criteria, and defines dynamic write ability as the critical pulse width for a write.
Abstract: This paper analyzes write ability for SRAM cells in deeply scaled technologies, focusing on the relationship between static and dynamic write margin metrics. Reliability has become a major concern for SRAM designs in modern technologies. Both local mismatch and scaled VDD degrade read stability and write ability. Several static approaches, including traditional SNM, BL margin, and the N-curve method, can be used to measure static write margin. However, static approaches cannot indicate the impact of dynamic dependencies on cell stability. We propose to analyze dynamic write ability by considering the write operation as a noise event that we analyze using dynamic stability criteria. We also define dynamic write ability as the critical pulse width for a write. By using this dynamic criterion, we evaluate the existing static write margin metrics at normal and scaled supply voltages and assess their limitations. The dynamic write time metric can also be used to improve the accuracy of VCCmin estimation for active VDD scaling designs.
175 citations
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