Book ChapterDOI
And-Exor Expressions and their Optimization
Tsutomu Sasao
- pp 287-312
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This chapter consists of two parts: the first part presents 7 classes of AND-EXOR expressions, and an optimization method for pseudo-ronecker expressions using ternary decision diagrams (TDDs).Abstract:
This chapter consists two parts: the first part presents 7 classes of AND-EXOR expressions:positive polarity Reed-Muller expressions, fixed polarity Reed-Muller expressions, Kronecker expressions, pseudo Reed-Muller expressions, pseudo Kronecker expressions, generalized Reed-Muller expressions and exclusive-or sum-of-products expressions (ESOPs) Relations between these classes are shown The number of products to realize several classes of functions are analyzed Optimization programs for these expressions were developed, and statistical results for arithmetic functions, randomly generated functions, and all the functions of 4 and 5 bariables were obtained The second part presents an optimization method for pseudo-ronecker expressions using ternary decision diagrams (TDDs) The conventional method requires memory of O(3n) to simplify an n-variable expression, and is only practical for functions of up to n = 14 variables The method presented here uses TDDs, and can optimize considerably larger problems Experimental results for up to n = 39 variables are shownread more
Citations
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Book ChapterDOI
An Optimized S-Box Circuit Architecture for Low Power AES Design
Sumio Morioka,Akashi Satoh +1 more
TL;DR: A low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields with hazard-transparent XOR gates located after the other gates that may block the hazards is proposed.
Journal ArticleDOI
EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions
TL;DR: A simplification algorithm that iteratively reduces the number of the products in ESOPs and then reduces theNumber of the literals is presented, used to replace a pair of products with another one.
Journal ArticleDOI
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture
S. Morioka,Akashi Satoh +1 more
TL;DR: A high-speed AES IP-core is presented, which runs at 880 MHz on a 0.13-/spl mu/m CMOS standard cell library, and which achieves over 10-Gbps throughput in all encryption modes, including cipher block chaining (CBC) mode.
Book
Spectral Interpretation of Decision Diagrams
TL;DR: This book discusses group-theoretic approach to optimization of DDs, as well as readings in DD on finite groups, signals, and Spectral techniques.
Proceedings ArticleDOI
A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture
S. Morioka,Akashi Satoh +1 more
TL;DR: A high-speed AES IP-core is presented, which runs at 780 MHz on a 0.
References
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