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Patent•

Apparatus for evaluating degradation of pattern features

21 Jan 2010-
TL;DR: A measurement tool for evaluating degradation of pattern features in a semiconductor device manufacturing process is described in this article.The measurement tool apparatus detects variations in the patterns from SEM images thereof and extracts pattern edge points along the circumference of each pattern.
Abstract: A measurement tool apparatus for evaluating degradation of pattern features in a semiconductor device manufacturing process. The measurement tool apparatus detects variations in the patterns from SEM images thereof and extracts pattern edge points along the circumference of each pattern. The measurement tool apparatus compares the pattern edge points to corresponding edge points of an ideal shape so as to determine deviation of the patterns. Metrics are derived from analysis of the deviations. The measurement tool apparatus uses the metrics in calculating an index representative of the geometry of edge spokes of the pattern, an indicator of the orientation of the edge spokes, and/or anticipated effects of the edge spokes on device performance.
Citations
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Patent•
19 Apr 2012
TL;DR: In this paper, a method for classification of semiconductor wafer patterns has been proposed based on topographical features of the location of interest in a 3D map of the area.
Abstract: A method for classification includes receiving an image of an area of a semiconductor wafer on which a pattern has been formed, the area containing a location of interest. At least one value for one or more attributes of the location of interest are computed based upon topographical features of the location of interest in a three-dimensional (3D) map of the area.

15 citations

Patent•
19 Apr 2012
TL;DR: In this article, a method for classification includes receiving an image of an area of a semiconductor wafer on which a pattern has been formed, the area containing an image location of interest, and receiving computer-aided design (CAD) data relating to the pattern comprising a CAD location corresponding to the image locations of interest.
Abstract: A method for classification includes receiving an image of an area of a semiconductor wafer on which a pattern has been formed, the area containing an image location of interest, and receiving computer-aided design (CAD) data relating to the pattern comprising a CAD location of interest corresponding to the image location of interest. At least one value for one or more attributes of the image location of interest is computed based on a context of the CAD location of interest with respect to the CAD data.

11 citations

Patent•
20 Jun 2019
TL;DR: In this article, a method for determining roughness of a feature in a pattern structure includes generating, using an imaging device, a set of one or more images, each including measured linescan information that includes noise, and then detecting edges of the features within the pattern structure of each image without filtering the images, generating a biased power spectral density (PSD) dataset representing feature geometry information corresponding to the edge detection measurements.
Abstract: Systems and methods are disclosed that remove noise from roughness measurements to determine roughness of a feature in a pattern structure. In one embodiment, a method for determining roughness of a feature in a pattern structure includes generating, using an imaging device, a set of one or more images, each including measured linescan information that includes noise. The method also includes detecting edges of the features within the pattern structure of each image without filtering the images, generating a biased power spectral density (PSD) dataset representing feature geometry information corresponding to the edge detection measurements, evaluating a high-frequency portion of the biased PSD dataset to determine a noise model for predicting noise over all frequencies of the biased PSD dataset, and subtracting the noise predicted by the determined noise model from a biased roughness measure to obtain an unbiased roughness measure.

7 citations

Patent•
18 Apr 2019
TL;DR: In this paper, a method for determining roughness of a feature in a pattern structure includes generating, using an imaging device, a set of one or more images, each including measured linescan information that includes noise, and then detecting edges of the features within the pattern structure of each image without filtering the images, generating a biased power spectral density (PSD) dataset representing feature geometry information corresponding to the edge detection measurements.
Abstract: Systems and methods are disclosed that remove noise from roughness measurements to determine roughness of a feature in a pattern structure. In one embodiment, a method for determining roughness of a feature in a pattern structure includes generating, using an imaging device, a set of one or more images, each including measured linescan information that includes noise. The method also includes detecting edges of the features within the pattern structure of each image without filtering the images, generating a biased power spectral density (PSD) dataset representing feature geometry information corresponding to the edge detection measurements, evaluating a high-frequency portion of the biased PSD dataset to determine a noise model for predicting noise over all frequencies of the biased PSD dataset, and subtracting the noise predicted by the determined noise model from a biased roughness measure to obtain an unbiased roughness measure.

6 citations

Patent•
30 May 2019
TL;DR: In this article, a method for determining roughness of a feature in a pattern structure includes generating, using an imaging device, a set of one or more images, each including measured linescan information that includes noise, and then detecting edges of the features within the pattern structure of each image without filtering the images, generating a biased power spectral density (PSD) dataset representing feature geometry information corresponding to the edge detection measurements.
Abstract: Systems and methods are disclosed that remove noise from roughness measurements to determine roughness of a feature in a pattern structure. In one embodiment, a method for determining roughness of a feature in a pattern structure includes generating, using an imaging device, a set of one or more images, each including measured linescan information that includes noise. The method also includes detecting edges of the features within the pattern structure of each image without filtering the images, generating a biased power spectral density (PSD) dataset representing feature geometry information corresponding to the edge detection measurements, evaluating a high-frequency portion of the biased PSD dataset to determine a noise model for predicting noise over all frequencies of the biased PSD dataset, and subtracting the noise predicted by the determined noise model from a biased roughness measure to obtain an unbiased roughness measure.

6 citations

References
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Journal Article•DOI•
Carlos H. Diaz, Hun-Jan Tao1, Yao-Ching Ku1, Anthony Yen1, K. Young1 •
TL;DR: In this article, an analytical model to represent line edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices is presented.
Abstract: This letter introduces an analytical model to represent line-edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices. The model partitions a given device into small unit cells along its width, each unit cell assumes a constant gate length (i.e., cell's width is small compared to LER spatial frequency). An analytical model is used to represent saturated threshold voltage dependency on the unit cell's gate length. Using this technique, an efficient and accurate model for LER effects (through V/sub ts/ variations) on off-state leakage and drive current is proposed and experimentally validated using 193 and 248 nm lithography for devices with 80-nm nominal gate lengths. Assuming that the deviation from the ideal 0-LER case remains constant from generation to generation, the model predicts that 3 nm or less LER is required for 50-60-nm state-of-the-art devices in the 0.1-/spl mu/m technology node. Based on data presented, we suggest that the LER requirement for this technology node is attainable with an alternated phase-shift type of patterning process.

178 citations

Proceedings Article•DOI•
P. Oldiges1, Qimghuamg Lin, K. Petrillo, Martha I. Sanchez, Meikei Ieong, Michael J. Hargrove •
06 Sep 2000
TL;DR: In this article, a fast method to estimate the effects of line edge roughness is proposed, based upon the use of multiple 2D device "slices" sandwiched together to form a MOS transistor of a given width.
Abstract: A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device "slices" sandwiched together to form a MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters.

158 citations

Patent•
02 May 2003
TL;DR: In this article, a statistical function of shape roughness is defined and a statistical perturbation is derived based on the statistical function and superimposed on the initial model to define a modified model of the structure.
Abstract: A simulated diffraction signal to be used in measuring shape roughness of a structure formed on a wafer using optical metrology is generated by defining an initial model of the structure. A statistical function of shape roughness is defined. A statistical perturbation is derived based on the statistical function and superimposed on the initial model of the structure to define a modified model of the structure. A simulated diffraction signal is generated based on the modified model of the structure.

43 citations

Patent•
10 Dec 2004
TL;DR: In this paper, a non-circular non-linear shape is fitted to the plurality of points on an edge of the feature in the image and a roughness parameter for the feature is computed in response to the respective distances.
Abstract: A method for evaluating a feature, consisting of receiving an image of the feature and determining respective coordinates of a plurality of points on an edge of the feature in the image. A figure having a non-circular non-linear shape is fitted to the plurality of points, and respective distances between the plurality of points and the figure are determined. A roughness parameter for the feature is computed in response to the respective distances. The method finds application in the analysis of critical dimensions (CD) of integrated circuits and, particularly, in the measurement of the edge roughness of their features and components as imaged by means of eg. The electron scanning microscopy (SEM).

18 citations

Proceedings Article•DOI•
24 May 2004
TL;DR: In this paper, the amplitude and frequency of contact hole edge roughness was measured using two CD-SEM algorithms, and these two metrics proved capable of detecting differences within four wafer pairs with varying dimension and processing.
Abstract: The edge roughness of straight lines has received intense focus in the past, whereas the edge roughness of contact holes has been relatively unexplored. Reductions in contact hole roughness can be shown to offer improvements in electrical breakdown voltages, or potentially the opportunity for reduced cellsize. This paper introduces two CD-SEM algorithms for characterizing the amplitude and frequency of contact hole edge roughness. When combined, these two metrics proved capable of detecting differences within four wafer pairs with varying dimension and processing. Increased roughness amplitude was shown to correlate to electrical breakdown failures.

12 citations