Architectural selection of A/D converters
02 Jun 2003-pp 974-977
TL;DR: It is shown that the calculated figures of merit of the published designs, together with the calculated global trade-off comprise a surface in the (5 dimensional) design space that makes it possible to accurately predict the power consumption and select the best converter solution for a certain target application.
Abstract: A method for the architectural selection of analog to digital (A/D) converters based on a generic figure of merit is described. First a figure of merit for the power consumption is introduced. This figure of merit includes both target specifications and technology data and has five generic parameters. The values of these generic parameters can be estimated by analyzing the different converter structures or by means of a fitting procedure using data from published designs. It is shown that the generic parameters have different values for different types of converters. Therefore the trade-off between speed, resolution, power dissipation and technology parameters depends on the type of converter. It is shown that the calculated figures of merit of the published designs, together with the calculated global trade-off comprise a surface in the (5 dimensional) design space. This surface makes it possible to accurately predict the power consumption and select the best converter solution for a certain target application. This can then serve as a first step in data converter synthesis or as a power estimator during high-level system design exploration.
Citations
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TL;DR: The purpose of this article is to enumerate some of the pertaining progress slopes, explain their possible foundations, and speculate about their remaining lifetime.
Abstract: At the turn of this century, there was widespread concern that the performance of analog-to-digital converters (ADCs) might have reached a saturation point and would, in fact, deteriorate as we began to scale into deep submicron CMOS technology. The past 15 years of innovation have clearly refuted such fears. Driven by a combination of application pull, architectural modifications, and relentless optimization, we have seen steady improvements in several key performance metrics.
120 citations
Cites background from "Architectural selection of A/D conv..."
...) have been proposed in the literature [4], [21], but their empirical and data-driven nature makes them difficult to use....
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TL;DR: A tradeoff between the power consumption of the system and the chip area in terms of the multiplexing ratio is investigated and the optimal number of channels per ADC is selected to achieve the minimum power-area product for the entire system.
Abstract: Power and chip area are the most important parameters in designing a neural recording system in vivo. This paper reports a design methodology for an optimized integrated neural recording system. Electrode noise is considered in determining the ADC's resolution to prevent over-design of the ADC, which leads to unnecessary power consumption and chip area. The optimal transconductance and gain of the pre-amplifiers, which minimizes the power-area product of the amplifier, are mathematically derived. A numerical example using actual circuit parameters is shown to demonstrate the design methodology. A tradeoff between the power consumption of the system and the chip area in terms of the multiplexing ratio is investigated and the optimal number of channels per ADC is selected to achieve the minimum power-area product for the entire system. Following the proposed design methodology, a chip has been designed in 0.35 mum CMOS process, with the multiplexing ratio of 16:1, resulting in total chip area of 2.5 mm times 2.0 mm and power consumption of 5.3 mW from plusmn1.65 V.
116 citations
13 Jun 2005
TL;DR: Effective logic soft error protection requires solutions to the following three problems: accurate soft error rate estimation for combinational logic networks; automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected.
Abstract: Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) accurate soft error rate estimation for combinational logic networks; (2) automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) new cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.
99 citations
TL;DR: Two simulation-based methods for the calculation of the feasible performance values of analog integrated circuits are presented, which allow a comparison of different circuit topologies with respect to their performance capabilities and contribute to hierarchical circuit sizing.
Abstract: This paper presents two simulation-based methods for the calculation of the feasible performance values of analog integrated circuits. The first method computes the Pareto-optimal tradeoffs of competing performances at full simulator accuracy. Additionally, it identifies and evaluates the technological and structural constraints that prevent further performance improvement. The second method computes linear approximations to the feasible performance regions of circuits with a large number of performances. Both techniques allow a comparison of different circuit topologies with respect to their performance capabilities and contribute to hierarchical circuit sizing. The presented methods are validated by experimental results of Pareto-front computation and feasible performance region computation of operational amplifiers and hierarchical sizing of filters.
64 citations
References
More filters
TL;DR: In this article, the design and implementation of a CMOS /spl Sigma/spl Delta/ modulator for digital-audio A/D conversion that operates from a single 1.8-V power supply is examined.
Abstract: Oversampling techniques based on sigma-delta (/spl Sigma//spl Delta/) modulation offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in low-voltage environment. This paper examines the design and implementation of a CMOS /spl Sigma//spl Delta/ modulator for digital-audio A/D conversion that operates from a single 1.8-V power supply. A cascaded modulator that maintains a large full-scale input range while avoiding signal clipping at internal nodes is introduced. The experimental modulator has been designed with fully differential switched-capacitor integrators employing different input and output common-mode levels and boosted clock drivers in order to facilitate low voltage operation. Precise control of common-mode levels, high power supply noise rejection, and low power dissipation are obtained through the use of two-stage, class A/AB operational amplifiers. At a sampling rate of 4 MHz and an oversampling ratio of 80, an implementation of the modulator in a 0.8-/spl mu/m CMOS technology with metal-to-polycide capacitors and NMOS and PMOS threshold voltages of +0.65 V and -0.75 V, respectively, achieves a dynamic range of 99 dB at a Nyquist conversion rate of 50 kHz. The modulator can operate from supply voltages ranging from 1.5-2.5 V, occupies an active area of 1.5 mm/sup 2/, and dissipates 2.5 mW from a 1.8-V supply.
239 citations
"Architectural selection of A/D conv..." refers background in this paper
...If it is assumed that the modulators performance is limited by thermal (kT C ) noise, it follows that the sampling capacitance of the first integrator should be [ 9 ]:...
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TL;DR: The design of a high-resolution high-speed delta-sigma analog-to-digital converter that operates from a single 3.3V supply is presented, which achieves a SNR of 87 dB, a SNDR of 82 dB and an input dynamic range of 15 bits after comb-filtering.
Abstract: The design of a high-resolution, high-speed, delta-sigma analog to-digital converter that operates from a single 3.3-V supply is presented. This supply voltage presents several design problems, such as reduced signal swing and nonzero switch resistance in the switched-capacitor circuits. These problems are tackled in this design by a careful optimization at the system level and by a detailed analysis of several circuit nonidealities. The converter uses a 2-1-1 cascade topology with optimized coefficients. For an oversampling-ratio of only 24, the converter achieves a signal-to-noise ratio of 87 dB, a signal-to-(noise+distortion) ratio of 82 dB, and an input dynamic range of 15 bits after comb filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for asymmetrical digital subscriber line applications of 1.1 MHz. It is implemented in a 0.5-/spl mu/m CMOS technology, in a 5-mm/sup 2/ die area, and consumes 200 mW from a 3.3-V power supply.
149 citations
"Architectural selection of A/D conv..." refers background in this paper
...Although this is true if the design is compared to some reference design that has a perfect scaled Cs, this seems never to be the case since designs that are compared with this figure of merit do not nearly reach the ideal [4]....
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...A good example of this is the Delta-Sigma modulator, that was originally thought of to be limited to low frequencies, but that has recently been used even in the megaHertz domain [4]....
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TL;DR: In this article, the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters is reviewed with respect to technology scaling, and a comparison is made between slew-rate dominated circuits and settling dominated circuits.
Abstract: In this paper the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters (ADCs) is reviewed with respect to technology scaling. The never-ending story of complementary metal-oxide-semiconductor (CMOS) technology trends toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Supply voltage scaling and mismatch scaling trends are discussed and it is shown that in future technologies the power consumption of matching-dominated high-speed ADCs will increase to achieve the same accuracy and speed. Also, a comparison is made between slew-rate dominated circuits and settling dominated circuits. Finally, a comparison with published high-speed ADCs is presented using the figure of merit.
140 citations
135 citations
"Architectural selection of A/D conv..." refers methods in this paper
...For oversampling ratios larger than two, the dynamic range of a Delta-Sigma modulator can be approximated by [1]:...
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05 May 1996
TL;DR: In this article, the influence of transistor mismatch on the trade-off between speed, accuracy and power consumption of basic building blocks and analog systems is investigated, and the ratio (Speed Accuracy/sup 2/)/Power for a circuit or system in CMOS is shown to be only dependent on technological constants which express the matching quality of the technology.
Abstract: The influence of transistor mismatch on the trade-off between speed, accuracy and power consumption of basic building blocks and analog systems is investigated. The ratio (Speed Accuracy/sup 2/)/Power for a circuit or system in CMOS is shown to be only dependent on technological constants which express the matching quality of the technology. Moreover, the minimal power consumption of high speed analog systems in CMOS imposed by transistor mismatch is two orders higher than the limit imposed by thermal noise.
124 citations
"Architectural selection of A/D conv..." refers background in this paper
...For the analog circuitry, an extra bit means a factor four increase in power, again because of matching considerations (this is the speed-accuracy power trade-off [6])....
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