Proceedings ArticleDOI
Area- and efficiency-optimized junction termination for a 5.6 kV SiC BJT process with low ON-resistance
Arash Salemi,Hossein Elahipanah,Gunnar Malm,Carl-Mikael Zetterling,Mikael Östling +4 more
- pp 249-252
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TLDR
In this paper, an area-optimized three-zone junction termination extension (O-JTE) is implemented, reducing the total area (and substrate cost) by about 30% compared to the traditional JTE designs.Abstract:
Implantation-free mesa-etched 4H-SiC bipolar junction transistors (BJTs) with a near-ideal breakdown voltage of 5.6 kV (about 92% of the theoretical value) are fabricated, measured and analyzed by device simulation. An efficient and optimized termination; area-optimized three-zone junction termination extension (O-JTE) is implemented, reducing the total area (and substrate cost) by about 30% compared to the traditional JTE designs. A maximum current gain of β = 44 at a current density of 472 A/cm2, and a specific on-resistance of R ON = 18.8 mΩ.cm2 is obtained for the device. The device shows a negative temperature coefficient of the current gain (β = 14.5 at 200 °C) and a positive temperature coefficient of on-resistance (R ON = 57.3 mΩ·cm2 at 200 °C).read more
Citations
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Journal ArticleDOI
15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain
TL;DR: In this paper, a mesa-etched ultra-high-voltage (0.08 mm2) 4H-SiC bipolar junction transistors with record current gain of 139 were fabricated, measured, and analyzed by device simulation.
Journal ArticleDOI
Optimal Emitter Cell Geometry in High Power 4H-SiC BJTs
TL;DR: In this paper, three 4H-SiC bipolar junction transistor designs with different emitter cell geometries (linear interdigitated fingers, square cell geometry, and hexagon cell geometry) are fabricated, analyzed, and compared with respect to current gain, ON-resistance, current density, and temperature performance for the first time.
Journal ArticleDOI
Intertwined Design: A Novel Lithographic Method to Realize Area Efficient High-Voltage SiC BJTs and Darlington Transistors
TL;DR: In this article, the authors proposed a novel lithographic method called intertwined design for high-power SiC devices to improve the area usage and current drive with more uniform current distribution along the device.
Proceedings ArticleDOI
State of the art power switching devices in SiC and their applications
TL;DR: The superior switching performance is discusses as well as the energy efficiency of SiC devices, focusing on high temperature capability such as integrated digital and analog circuits up to 600 C.
Journal ArticleDOI
Conductivity Modulated and Implantation-Free 4H-SiC Ultra-High-Voltage PiN Diodes
TL;DR: In this paper, an implantation-free mesa etched ultra-high-voltage 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation.
References
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BookDOI
Fundamentals of Power Semiconductor Devices
TL;DR: In this article, the fundamental physics of power semiconductor devices are discussed and an analytical model for explaining the operation of all power Semiconductor devices is presented, focusing on silicon devices.
Journal ArticleDOI
21-kV SiC BJTs With Space-Modulated Junction Termination Extension
TL;DR: In this article, a 20kV-class small area (0.035 mm2) 4H-SiC bipolar junction transistors were implemented with edge termination techniques featuring two-zone junction termination extension and space-modulated rings.
Journal ArticleDOI
Surface-Passivation Effects on the Performance of 4H-SiC BJTs
Reza Ghandi,Benedetto Buono,Martin Domeij,Romain Esteve,Adolf Schöner,Jisheng Han,Sima Dimitrijev,Sergey A. Reshanov,C.-M. Zetterling,Mikael Östling +9 more
TL;DR: In this article, the performance of bipolar junction transistor (BJT) is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface passivation layers.
Journal ArticleDOI
High-Voltage 4H-SiC PiN Diodes With Etched Junction Termination Extension
TL;DR: In this paper, mesa-etched 4H-SiC PiN diodes with a near-ideal breakdown voltage of 4.3 kV were fabricated, measured, and analyzed by device simulation and optical imaging measurements at breakdown.