Area and power efficient network on chip router architecture
11 Apr 2013-pp 855-859
TL;DR: This paper has implemented a 5-port 32-bit and 64-bit router architecture using wormhole routing technique for 2D-mesh network by using simple deterministic algorithm, flow control and decoding mechanism and demonstrated that multiplexer router design is more efficient than a matrix router design.
Abstract: In System on Chip, buses and point to point links are used as a communication infrastructure between one IP to another, but these cannot provide efficient interconnect from performance point of view. So NoC architecture was proposed to provide communication in multiprocessor SoC and overcome the limitations. This paper has implemented a 5-port 32-bit and 64-bit router architecture using wormhole routing technique for 2D-mesh network by using simple deterministic algorithm, flow control and decoding mechanism. In this router, 2 types of crossbar are used named as multiplexer and tri-state buffer matrix for efficient design. Comparisons of area and power are done for these router designs using ASIC tool flow in Cadence using TSMC 90nm and 180nm process technologies. Simulation results are performed in Cadence NC simulator. It is demonstrated that multiplexer router design is more efficient than a matrix router design as area and power increases for matrix design while using same port-width.
Citations
More filters
TL;DR: The exemplary real world application, video object plane decoder is mapped on a 2D mesh NoC using different mapping algorithms under NOCMAP and NoCTweak simulators for comparative analysis of the NoC simulators and their embedded mapping algorithms.
Abstract: Network-on-chip (NoC) is a reliable and scalable communication paradigm deemed as an alternative to classic bus systems in modern systems-on-chip designs. Consequently, one can observe extensive multidimensional research related to the design and implementation of NoC-based systems. A basic requirement for most of these activities is the availability of NoC simulators that enable the study and comparison of different technologies. This study targets the analysis of different NoC simulators and highlights its contributions towards NoC research. Various NoC tools such as NoCTweak, Noxim, Nirgam, Nostrum, BookSim, WormSim, NOCMAP and ORION are evaluated and their strengths and weaknesses are highlighted. The comparative analysis includes methods for estimation of latency, throughput and energy consumption. Further, the exemplary real world application, video object plane decoder is mapped on a 2D mesh NoC using different mapping algorithms under NOCMAP and NoCTweak simulators for comparative analysis of the NoC simulators and their embedded mapping algorithms.
24 citations
25 Jul 2017
TL;DR: Novel two-level and tree-like multiplexer structures intended for low-power applications based on Silicon Nanowire TIGFETs (TIG SiNWFets) are presented and compared with conventional CMOS FinFET Low-STandby Power (LSTP) structures.
Abstract: Three-Independent-Gate Field Effect Transistors (TIGFETs) are capable of different modes of operation thanks to their additional gate terminals. By electrically controlling their side gates, TIGFETs can act either as a p-type or an n-type transistor and can also implement multi-threshold logic. This versatility can be used to create compact logic gates intended for high-performance or low-leakage applications. In today's Integrated Circuits (ICs), multiplexers are used in a broad range of applications such as encoding-decoding, routing signals or Look-Up Tables (LUTs). In particular, conventional Complementary Metal-Oxide-Semiconductor (CMOS)-based multiplexers with a large number of inputs require several stages, leading to significant area and energy. Due to their three-gate terminals, TIGFETs can implement the equivalent multiplexers using less transistors, arranged in a compact way, reducing the area and energy. In this paper, we present novel two-level and tree-like multiplexer structures intended for low-power applications based on Silicon Nanowire TIGFETs (TIG SiNWFETs) and compare it with conventional CMOS FinFET Low-STandby Power (LSTP) structures. Using the 22nm technology node, electrical simulations show that our SiNWFET-based multiplexer can improve the energy by operation by 2 5× and Energy-Area Product by up to 2.6× compared to the best CMOS FinFET structures.
20 citations
15 May 2015
TL;DR: Results show that the proposed design consumes less power compared to the previously designed reconfigurable routers, and power dissipation of the proposed reconfigured router is reduced using Power gating technique.
Abstract: FPGA based design of reconfigurable router for NoC applications is proposed in the present work. Design entry of the proposed router is done using Verilog Hardware Description Language (Verilog HDL). The router designed in the present work has four channels (namely, east, west, north and south) and a crossbar switch. Each channel consists of First in First out (FIFO) buffers and multiplexers. FIFO buffers are used to store the data and the input and output of the data are controlled using multiplexers. Firstly, south channel is designed which includes the design of FIFO and multiplexers. After that, the crossbar switch and other three channels are designed. All these designed channels, FIFO buffers, multiplexers and crossbar switches are integrated to form the complete router architecture. The proposed design is simulated using Modelsim and the RTL view is obtained using Xilinx ISE 13.4. Xilinx SPARTAN-6 FPGAs are used for synthesis of proposed design. Power dissipation of the proposed reconfigurable router is reduced using Power gating technique. Total power is calculated by the use of XPower Analyzer tool. Obtained results show that the proposed design consumes less power compared to the previously designed reconfigurable routers.
13 citations
Cites background or methods from "Area and power efficient network on..."
...A router having eight input ports and one output port for Network on Chip using IP core with latest verification methodologies are presented in [12]....
[...]
...Multiplexer based crossbar switch for 5 ports [12]....
[...]
TL;DR: The mapping results of the exemplary real world applications indicate that the proposed ONMAP algorithm is more efficient than its competitors for most of the performance parameters of the on-chip network designs.
Abstract: In this paper, we propose an optimized, search based near-optimal mapping heuristic, named as ONMAP for mapping real time embedded application workloads on 2D based on-chip interconnection network platforms. ONMAP exploits NMAP, a well-known and fast nearest neighbor heuristic algorithm by using the modular exact optimization method. The proposed hybrid algorithm minimizes the on-chip inter-processor communication energy consumption and optimizes the interconnection network performance parameters. The algorithm inherits the constructive search based heuristic nature of the NMAP algorithm, as well as the property of exact optimization for mapping embedded applications on the target communication architecture. To verify the efficiency and effectiveness of the algorithm, we have compared the proposed algorithm with NMAP and random mapping algorithm under similar simulation environments and traffic conditions. The mapping results of the exemplary real world applications such as VOPD, PIP, MPEG4, MWD, MMS and WiFi-80211arx indicate that ONMAP algorithm is more efficient than its competitors for most of the performance parameters of the on-chip network designs. The algorithm successfully optimized the energy consumption, up to 20 % and 26% in comparison to NMAP and random algorithms, respectively. Similarly, the cost is optimized up to 10% and 60% as compared to NMAP and random mapping algorithms, respectively.
9 citations
01 Sep 2018
TL;DR: There is a strong correlation between SoC characteristics and good NoC design practices, however this correlation is highly non-linear and multidimensional, with dimensions indicative of the features of the SoC, design goals and properties of the NoC.
Abstract: Modern System on Chips (SoCs) are becoming increasingly complex with a growing number of CPUs, caches, accelerators, memory and I/O subsystems. For such designs, a packet based distributed networks-on-chip (NoCs) interconnect can provide scalability, performance and efficiency. However, the design of such a NoC involves optimizing a large number of variables such as topology, routing choices, arbitration and quality of service (QoS) policies, buffer sizes, and deadlock avoidance policies. Widely varying die sizes, power, floorplan and performance constraints across a variety of different market segments, ranging from high-end servers to low-end IoT devices, impose additional design challenges. In this paper we demonstrate that there is a strong correlation between SoC characteristics and good NoC design practices. However this correlation is highly non-linear and multidimensional, with dimensions indicative of the features of the SoC, design goals and properties of the NoC. This results in a high-dimensional NoC design space and complex search process which is inefficient to solve with classic algorithms. Using a variety of real SoCs and training data sets, we demonstrate that a machine learning (ML) based approach yields near-optimal NoC designs quickly. We determine a number of SoC and NoC features, describe reduction methods, and also show that a multi-model approach yields better designs. We demonstrate that for a wide variety of SoCs, ML based NoC designs are far superior to those designed and optimized manually over years on almost all quality metrics.
6 citations
Cites background from "Area and power efficient network on..."
...consumption and efficient power management schemes [22][23][24][25] such as clock gating are an important aspect of interconnect construction....
[...]
References
More filters
Book•
01 Oct 1997
TL;DR: The book's engineering approach considers the issues that designers need to deal with and presents a broad set of practical solutions that address the challenges and details the basic underlying concepts of interconnection networks.
Abstract: From the Publisher:
Addresses the challenges and details the basic underlying concepts of interconnection networks. The book's engineering approach considers the issues that designers need to deal with and presents a broad set of practical solutions. Considerable effort is made to establish new and more.
2,021 citations
"Area and power efficient network on..." refers background in this paper
...circuit switching, packet switching, and wormhole switching [8]....
[...]
01 Jan 2000
TL;DR: This paper presents an architectural study of a scalable system-level interconnection template, and discusses the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services.
Abstract: This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not meet the performance requirements of tomorrow's systems. We present an alternative interconnection in the form of switching networks. This technology originates in parallel computing, but is also well suited for heterogeneous communication between embedded processors and addresses many of the deep submicron integration issues. We discuss the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services. Eventually we present our first results on the cost/performance assessment of an integrated switching network.
995 citations
"Area and power efficient network on..." refers methods in this paper
...Here are most popular ones: SPIN [3], CLICHÉ [4], TORUS [5], OCTAGON [6], and BFT [7]....
[...]
TL;DR: The octagon on-chip communication architecture, with its cost, performance, and scalability advantages, supports network processor SOCs of next-generation internet routers.
Abstract: Network processor systems on chips meet the speed and flexibility requirements of next-generation internet routers. The octagon on-chip communication architecture, with its cost, performance, and scalability advantages, supports these network processor SOCs.
293 citations
"Area and power efficient network on..." refers methods in this paper
...Here are most popular ones: SPIN [3], CLICHÉ [4], TORUS [5], OCTAGON [6], and BFT [7]....
[...]
10 May 2009
TL;DR: In this paper, the authors explore using photonics to implement low-diameter non-blocking crossbar and Clos networks, and show that a 64-tile photonic Clos network consumes significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters.
Abstract: Future manycore processors will require energy-efficient, high-throughput on-chip networks. Silicon-photonics is a promising new interconnect technology which offers lower power, higher bandwidth density, and shorter latencies than electrical interconnects. In this paper we explore using photonics to implement low-diameter non-blocking crossbar and Clos networks. We use analytical modeling to show that a 64-tile photonic Clos network consumes significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters. Compared to various electrical on-chip networks, our simulation results indicate that a photonic Clos network can provide more uniform latency and throughput across a range of traffic patterns while consuming less power. These properties will help simplify parallel programming by allowing the programmer to ignore network topology during optimization.
290 citations
25 May 2003
TL;DR: A switch-based network-centric architecture to interconnect IP blocks is proposed with a butterfly fat tree architecture as an overall interconnect template and wormhole routing is adopted to reduce overall latency and hardware overhead.
Abstract: System on Chip (SoC) design in the forthcoming billion transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks Some of the main problems in the ultra deep sub micron technologies characterized by gate lengths in the range of 50-100 nm arise from non-scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues, and difficulties associated with non-scalable bus-based functional interconnect These problems are addressed in this paper by introducing a new design methodology A switch-based network-centric architecture to interconnect IP blocks is proposed We introduce a butterfly fat tree architecture as an overall interconnect template In this new interconnect architecture, switches are used to transfer data between IP blocks To reduce overall latency and hardware overhead, wormhole routing is adopted The proposed switch architecture supports this routing method Initial implementation of the switch reveals that the total switch area is expected to amount to less than 2% of a large SoC
223 citations