Area-time-power tradeoffs in parallel adders
Citations
458 citations
Cites background from "Area-time-power tradeoffs in parall..."
...Comparison of the unit-gate model area/delay results with precise transistor-level synthesis results [31] show that this model yields acceptable relative accuracy at a high abstraction level using only simple analytic calculations [30]....
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349 citations
Cites background from "Area-time-power tradeoffs in parall..."
...…a Booth encoder for the generation of a reduced number of partial products; a carry save structured accumulator for a further reduction of the partial products’ matrix to only the addition of two operands; and a fast carry propagation adder (CPA) [9] for the computation of the final binary…...
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268 citations
84 citations
Cites methods from "Area-time-power tradeoffs in parall..."
...Adders are further optimized using carry-save method [11]- [12]....
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82 citations
Cites background or methods from "Area-time-power tradeoffs in parall..."
...Multi processor system on chip (MPSoC) is another design of choice for many modern high throughput signal processing and multimedia applications [10, 11]....
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...15 format end always @( posedge clk) begin prod[0] < xn[0] * b0; prod[1] < xn[2] * b1; prod[2] < xn[4] * b2; prod[3] < xn[6] * b3; prod[4] < xn[8] * b4; prod[5] < xn[10] * b5; prod[6] < xn[12] * b6; prod[7] < xn[14] * b7; end always @(posedge clk) begin mac[0] < prod[0]; for (i 0; i<7; i i+1) mac[i+1] < mac[i]+prod[i+1]; end assign yn mac[7]; endmodule...
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...This design methodology is discussed in [10] and [11]....
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...This is especially true formore complex signal processing applicationswherekeeping thenumerical accuracy intact is consideredcritical [10]....
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...A high speed bus like Amba High speed Bus (AHB) is used in these systems [10]....
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References
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