Book ChapterDOI
Asynchronous On-Line Monitoring of Logical and Temporal Assertions
Katell Morin-Allory,Laurent Fesquet,Benjamin Roustan,Dominique Borrione +3 more
- Vol. 10, pp 243-253
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TLDR
The synthesis of PSL assertions into asynchronous hardware monitors that can be linked to the circuit under monitoring is presented, based on a systematic interconnection of asynchronous primitive monitors corresponding to PSL operators.Abstract:
PSL is a standard formal language to specify logical and temporal properties under the form of assertions. This paper presents the synthesis of PSL assertions into asynchronous hardware monitors that can be linked to the circuit under monitoring. The checker synthesis is based on a systematic interconnection of asynchronous primitive monitors corresponding to PSL operators. The asynchronous monitors are implemented with quasi delay insensitive logic which gives reliable and robust monitors in the case of truly asynchronous events, temperature or voltage variations. These monitors are applicable to a wider range of verification tasks such as the communications among globally asynchronous modules or in safe or secure applications.read more
Citations
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Proceedings ArticleDOI
Verification of analog and mixed signal designs using online monitoring
TL;DR: This paper presents a methodology for the specification and verification of AMS designs using online monitoring at runtime based on the notion of System of Recurrence Equations (SREs), and implements the proposed methodology in a C language based tool and utilizes it to verify several properties of a PLL design.
Dissertation
Runtime Verification of Analog and Mixed Signal Designs
TL;DR: In this paper, the authors proposed a methodology for the verification of AMS designs using functional and statistical runtime verification using Monte Carlo simulation for the hypothesis test and for evaluating its performance.
Journal ArticleDOI
System-Level Observation Framework for Non-Intrusive Runtime Monitoring of Embedded Systems
Jong Chul Lee,Roman Lysecky +1 more
TL;DR: A system-level observation framework that provides minimally intrusive methods for dynamically monitoring and analyzing deeply integrated hardware and software components within embedded systems.
Proceedings ArticleDOI
Hardware Observability Framework for Minimally Intrusive Online Monitoring of Embedded Systems
TL;DR: This paper presents an initial framework for minimally intrusive hardware observability that provides designers with the ability to monitor complex application-specific hardware execution behavior at runtime with zero -- or minimal -- impact on system execution.
Dissertation
Vérification semi-formelle et synthèse automatique de circuits à partir de spécifications temporelles écrites en PSL
TL;DR: In this article, a methode de synthese de proprietes is proposed for verification of circuit complexes, which is modulaire, a base d'automates a ete developpee en collaboration with l'universite de McGill.
References
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Book
Principles of Asynchronous Circuit Design: A Systems Perspective
Jens Spars,Steve Furber +1 more
TL;DR: Industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.
Book
Assertion-Based Design
TL;DR: The focus of Assertion-Based Design, Second Edition is three-fold: how to specify assertions, how to create and adopt a methodology that supports assertion-based design, and what to do with the assertions and methodology once you have them.
Journal Article
PSL model checking and run-time verification via testers
Amir Pnueli,Anna Zaks +1 more
TL;DR: Besides providing the construction of testers for PSL, it is indicated how the symbolic representation of the testers can be directly utilized for efficient model checking and run-time monitoring.
Journal Article
FoCs: Automatic generation of simulation checkers from formal specifications
TL;DR: Formal Checkers (FoCs) as mentioned in this paperormal checkers can be used for model checking of small design blocks as well as for simulation analysis across all higher simulation levels.
Book ChapterDOI
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
TL;DR: For the foreseeable future, industrial hardware design will continue to use both simulation and model checking in the design verification process, with little cross-leverage of the individual advantages of simulation and formal verification.