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Journal ArticleDOI

Au/CdS Schottky Diode Fabricated with Nanocrystalline CdS Layer

01 Oct 1997-Physica Status Solidi (a) (WILEY‐VCH Verlag)-Vol. 163, Iss: 2, pp 433-443
TL;DR: In this paper, Schottky diodes of structure Au/nano-CdS/CBD-CDS/SnO 2 were fabricated with the nanocrystalline CdS layer deposited by the high pressure magnetron sputtering technique.
Abstract: Schottky diodes of structure Au/nano-CdS/CBD-CdS/SnO 2 were fabricated with the nanocrystalline CdS layer deposited by the high pressure magnetron sputtering technique. The devices were characterized by current-voltage (I-V) anti capacitance-voltage (C-V) measurements. It was observed that the presence of a large amount of surface states might explain the high values of n in the nano-devices. The quantization effects of the active nano-CdS layer in the devices was confirmed from the observed peaks in the plot of conductance versus reverse bias voltage.
Citations
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Journal ArticleDOI
TL;DR: The presence of a shallow acceptor in the CdSe quantum dots is found by means of a detailed impedance and Mott-Schottky (C(-2)-phi) study and it is clearly shown that this acceptor density decreases strongly with increasing quantum dot size.
Abstract: To enhance efficiencies of quantum dot CdSe/TiO2 based solar cells, understanding of the space charge at the CdSe/TiO2 interface is crucial. In this paper, the presence of a shallow acceptor in the CdSe quantum dots is found by means of a detailed impedance and Mott−Schottky (C−2−ϕ) study. Furthermore, it is clearly shown that this acceptor density decreases strongly with increasing quantum dot size. The presence of these defect states may give rise to Auger recombination in small quantum dots and therewith decrease the efficiency of quantum-dot-sensitized solar cells.

67 citations

Journal ArticleDOI
TL;DR: In this article, a metal-insulator-semiconductor (MIS) structure was identified by low temperature current-voltage measurements, which allowed the authors to identify the contact as a metal/insulator/semiconducting (MISO) structure.
Abstract: Electrical contacts to porous silicon were formed by depositing various metals such as aluminum, gold, and titanium onto its surface. Low temperature current–voltage measurements were performed, which allowed us to identify the contact as a metal–insulator–semiconductor (MIS) structure. The parameters which characterize the MIS structure: the mean barrier height presented by the insulating film (χ), the barrier height presented to the electrons in the metal by the semiconductor itself (VB0), the ideality coefficient (n) and the series resistance (Rs), were determined for each type of contact studied. All of these contacts show fairly high values of the ideality coefficient, which are explained by the presence of a large concentration of interface states.

30 citations

Journal ArticleDOI
TL;DR: In this paper, the fabrication and characterization of Al/PVA:n-CdS (MS) and Al/Al2O3/pVA: n-Ccds (MIS) diode were investigated using forward and reverse bias I-V, C-V and G/w-V characteristics at room temperature.
Abstract: This paper presents the fabrication and characterization of Al/PVA:n-CdS (MS) and Al/Al2O3/PVA:n-CdS (MIS) diode. The effects of interfacial insulator layer, interface states (N ss ) and series resistance (R s ) on the electrical characteristics of Al/PVA:n-CdS structures have been investigated using forward and reverse bias I–V, C–V, and G/w–V characteristics at room temperature. Al/PVA:n-CdS diode is fabricated with and without insulator Al2O3 layer to explain the effect of insulator layer on main electrical parameters. The values of the ideality factor (n), series resistance (R s ) and barrier height (ϕ b ) are calculated from ln(I) vs. V plots, by the Cheung and Norde methods. The energy density distribution profile of the interface states is obtained from the forward bias I–V data by taking into account the bias dependence ideality factor (n(V)) and effective barrier height (ϕ e ) for MS and MIS diode. The N ss values increase from mid-gap energy of CdS to the bottom of the conductance band edge for both MS and MIS diode.

29 citations

Journal ArticleDOI
TL;DR: In this paper, a mesoporous aerogel composed of cadmium sulfide nanoparticles partially modified with metallic gold (CdS-Au) is reported, where the semiconductor-metal nanoparticles are synthesized using an inverse micelle media of Bis-(2-ethylhexyl)sulfosuccinate sodium salt (AOT) in heptane, followed by capping with 4-fluorothiophenol and precipitation with triethylamine.
Abstract: Monolithic aerogels composed of cadmium sulfide nanoparticles partially modified with metallic gold (CdS-Au) are reported. The semiconductor–metal nanoparticles are synthesized using an inverse micelle media of Bis-(2-ethylhexyl)sulfosuccinate sodium salt (AOT) in heptane, followed by capping with 4-fluorothiophenol and precipitation with triethylamine. The nanoparticles are then dispersed in acetone and gel formation is achieved using nanoparticle condensation strategy. The resultant CdS-Au aerogel materials are mesoporous, with an interconnected network of semiconductor–metal nanoparticles. A detailed microstructure analysis of the semiconductor–metal aerogels via transmission electron microscopy indicates that the final gold concentration significantly impacts the semiconductor–metal aerogel morphology and porosity.

25 citations

Journal ArticleDOI
TL;DR: In this article, the effects of low substrate temperature on the currentvoltage (I-V ) characteristics of the Cu/CdS/SnO 2 structure were investigated in the temperature range 100-300 K.
Abstract: Polycrystalline CdS samples on the SnO 2 coated glass substrate were obtained by vacuum evaporation method at low substrate temperatures ( T S =200 and 300 K) instead of the commonly used vacuum evaporation at high substrate temperatures ( T S >300 K). X-ray diffraction studies showed that the textures of the films are hexagonal with a strong (0 0 2) preferred direction. Circular Cu contacts were deposited on the upper surface of the CdS thin films at 200 K by vacuum evaporation. The effects of low substrate temperature on the current–voltage ( I – V ) characteristics of the Cu/CdS/SnO 2 structure were investigated in the temperature range 100–300 K. The Cu/CdS (at 300 K)/SnO 2 structure shows exponential current–voltage variations. However, I – V characteristics of the Cu/CdS (at 200 K)/SnO 2 structure deviate from exponential behavior due to high series resistance. The diodes show non-ideal I – V behavior with an ideality factor greater than unity. The results indicate that the current transport mechanism in the Cu/CdS (at 300 K)/SnO 2 structure in the whole temperature range is performed by tunneling with E 00 =143 meV. However, the current transport mechanism in the Cu/CdS (at 200 K)/SnO 2 structure is tunneling in the range 200–300 K with E 00 =82 meV.

14 citations

References
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Journal ArticleDOI
TL;DR: In this paper, a theoretical and experimental study has been made of silicon Schottky diodes in which the metal and semiconductor are separated by a thin interfacial film.
Abstract: A theoretical and experimental study has been made of silicon Schottky diodes in which the metal and semiconductor are separated by a thin interfacial film. A generalized approach is taken towards the interface states which considers their communication with both the metal and the semiconductor. Diodes were fabricated with interfacial films ranging from 8 to 26 A in thickness, and their characteristics are related to this model. The effects of reduced transmission coefficients together with fixed charge in the film are investigated. The interpretation of the current-voltage characteristics and the validity of the C−2-V method in the determination of diffusion potentials are discussed.

1,519 citations

Journal ArticleDOI
TL;DR: In this article, it was shown that a reliable value of the barrier height can be obtained even if there is a series resistance which would hamper the evaluation of the standard lnI•vs•V plot.
Abstract: It is shown that by plotting the function F (V) =V/2−(kT/q) ln(I/AA**T2) a reliable value of the barrier height can be obtained even if there is a series resistance which would hamper the evaluation of the standard lnI‐vs‐V plot. A theoretical examination of F (V) is followed by experimental plots for some common Schottky‐barrier diodes.

1,246 citations

Journal ArticleDOI
TL;DR: In this paper, a three-dimensional semiconductor quantum well (quantum dot) has been investigated and the fine structure observed in resonant tunneling through the quantum dot corresponds to the discrete density of states of a zero-dimensional system.
Abstract: Electronic transport through a three-dimensionally confined semiconductor quantum well (``quantum dot'') has been investigated. Fine structure observed in resonant tunneling through the quantum dot corresponds to the discrete density of states of a zero-dimensional system.

886 citations

Journal ArticleDOI
TL;DR: In this paper, the authors proposed and examined three different plots for the determination of the saturation current, the ideality factor, and the series resistance of Schottky diodes and solar cells from the measurement of a single current (I)/voltage (V) curve.
Abstract: This paper proposes and examines three different plots for the determination of the saturation current, the ideality factor, and the series resistance of Schottky diodes and solar cells from the measurement of a single current (I)/voltage(V) curve. All three plots utilize the small signal conductance and avoid the traditional Norde plot completely. A test reveals that the series resistance and the barrier height of a test diode can be determined with an accuracy of better than 1%. Finally it is shown that a numerical agreement between measured and fittedI/V curves is generally insufficient to prove the physical validity of current transport models.

408 citations